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PDF TXC-03103C Data sheet ( Hoja de datos )
| Número de pieza | TXC-03103C | |
| Descripción | Quad T1 Framer Plus | |
| Fabricantes | Transwitch | |
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QT1F-Plus Device
m Quad T1 Framer-Plus
.co TXC-03103C
t4U DATA SHEET
heeFEATURES
S• D4 SF, ESF (including HDLC Link support), and
tatransparent framing modes
a• Encodes/decodes AMI/B8ZS and forced ones
.Ddensity line codes
w• Fractional T1 gapped clock
w• Monitor function for frame pulse, clock and data
w• Two-frame slip buffers in both receive and transmit
directions
m• Supports channel associated and robbed-bit
osignaling (enabled or processor forced on a per
DS0 basis)
.c• Detects and forces Yellow and AIS alarms; detects
OOF, Severely Errored Frame, and Change of
Frame Alignment, detects AIS-CI
U• Detects, counts and forces line code errors (BPVs
t4and excess zeros), CRC errors (ESF only), and
frame bit errors
e• Motorola/Intel compatible microprocessor
interface
e• One-second interrupt input latches counter values
and line events into shadow registers
h• Local, line remote, payload remote and DS0
channel loopbacks, per DS0 channel inversion
S• Processor forcing/monitoring of DS0s for
tamaintenance purposes
• Boundary scan capability (IEEE 1149.1)
a• Single +3.3 volt or +5.0 volt power supply
• 128-pin low profile plastic quad flat package
DESCRIPTION
The QT1F-Plus (TXC-03103C) is a four-channel DS1 (T1,
1.544 Mbit/s) framer designed with extended features for
voice and data communications applications. AMI, B8ZS,
and NRZ line codes are supported with full alarm detection
and generation per ANSI T1M1.3. The transmit and receive
sections of each of the four framers are independent, with
individual slip buffers to allow operation in a wide range of
switching and transmission products. D4 SF and ESF
modes are provided per ANSI T1.403-1998 and AT&T PUB
62411, with per DS0 signaling and DS0 data access and
control via a Motorola/Intel-compatible microprocessor
interface. For ESF applications, each framer supplies a full
duplex HDLC/bit-oriented message controller, supporting
back-to-back FDL messages in addition to onboard latching
of all required performance parameters; minimal software
overhead is required to support either ANSI T1.403-1998 or
AT&T PUB 54016 protocols. Diagnostic, test, and
maintenance functions are provided, including four loopback
modes and boundary scan (IEEE 1149.1).
APPLICATIONS
• SONET/SDH terminal or add/drop multiplexers
supporting DS1 byte synchronous operation
• DCS, digital central office or remote digital terminals
• T1 multiplexers
• T1 and fractional T1 CSUs
• ATM products with integrated DS1 interfaces
• LAN routers with integrated DS1 interfaces
• Multichannel DS1 test equipment
• Internet Access Equipment with T1 and Fractional T1
Interfaces
.DLINE SIDE
wDS1 Dual
wRail / NRZ
Data & Clocks
w .comInterrupt/Select
UTransceiver
t4Serial Interface
4x3
4x3
4x2
QT1F-Plus
Quad T1 Framer-Plus
TXC-03103C
SYSTEM (TERMINAL) SIDE
4x4
4x4
NRZ Data
and Signaling
Highways
System I/O
Clocks
SheeIEEE 1149.1
System &
Microprocessor
ta(JTAG) Interface Fallback Clocks
Interface
U.S. Patent No. 5,615,237 and 6,456,595
aCopyright 2004 TranSwitch Corporation
.DPHAST, TEMx28, TranSwitch and TXC are
registered trademarks of TranSwitch Corporation
wMVIP is a registered trademark of GO-MVIP, Inc.
Document Number:
PRELIMINARY TXC-03103C-MB, Ed. 3
October 2004
wwTranSwitch Corporation • 3 Enterprise Drive • Shelton, Connecticut 06484 • USA
Tel: 203-929-8810 • Fax: 203-926-9453 • www.transwitch.com
1 page  
Proprietary TranSwitch Corporation Information for use Solely by its Customers
DATA SHEET
QT1F-Plus
TXC-03103C
Fractional T1:
• Gapped Clock programmed DS0 channels
• Receive and Transmit gapped clocks with selection and direction independent
DS0 Control:
• Per DS0 enable (independent receive and transmit) with microprocessor read and
substitution in both receive and transmit directions
• Per DS0 inversion in transmit and receive directions (after slip buffer) in both Transmission
and MVIP Modes.
Maintenance:
• Loopbacks - line remote, local, payload remote (ESF only) and DS0 channel
• Detect and transmit SF loop-up and loop-down codes
• Full duplex HDLC link controller with bit-oriented code support for HDLC link and 16-byte receive
and transmit FIFOs, back-to-back message support
• Boundary Scan (IEEE 1149.1) for input/output pin monitoring
Microprocessor Interface:
• Eight-bit status register for LOS, AIS, OOF, YEL, CFA, SEF, TXSLIP and RXSLIP
• Eight-bit latched event register and interrupt mask register
• CRC (ESF only), code violation and frame bit error counters
• Shadow registers and counters
• Full control of framing, alarm generation and propagation, codec features
• HDLC link control, signaling access/control, DS0 access/control
• Reset, resync, slip buffer and frame bit access
The following features are only selectable for the four framers as a group:
• Transmission Mode ("off line" framing) or MVIP Mode system interfaces
• Serial port to read/write control up to four line interface transceivers, or selection of one of four DS1
line interfaces (receive or transmit) to monitor clock, frame pulse and data
• Microprocessor global reset, masks, polling registers, interrupt polarity and latch edge control
• Two reference clock outputs at 8kHz or 1544 kHz with freeze on LOS
• IEEE 1149.1 boundary scan
• Motorola or Intel microprocessor access with separate address and data buses
• Ability to tristate all outputs for in-circuit testing
• Ability to place line side transmit clock and data to logic low for protection switching
• Synchronization start position is programmable to any receive or transmit bit position on the system
side
• External shadow register clock input
• Pseudo-Random Binary Sequence (PRBS) generator and analyzer
Enhancements over the Quad T1 Framer-Plus TXC-03103:
• SF mode 9-state signaling for ANSI T-403 Rob and limited support for SLC-96 applications
• Per DS0 inversion in Transmission and MVIP modes
• Frame bits available in MVIP mode, and supports bypass FDL feature in MVIP mode
• AIS-CI detector
• FDL back-to-back message support
- 5 of 156 -
PRELIMINARY TXC-03103C-MB, Ed. 3
October 2004
5 Page 
Proprietary TranSwitch Corporation Information for use Solely by its Customers
DATA SHEET
QT1F-Plus
TXC-03103C
PIN DESCRIPTIONS
Power Supply and Ground
Symbol
Pin No.
I/O/P*
VDD
GND
14, 25, 45, 57,
78, 89, 116
20, 30, 44, 47, 52, 73,
84, 94, 111, 121, 124
P
P
* Note: I = Input; O = Output; P = Power; T=Tristate.
Type
Name/Function
Power Supply: +3.3 or +5.0 volt, ±5%, VDD supply
voltage.
Ground: 0 volt reference.
Line Interface Signals
Symbol Pin No. I/O/P
RPOSn/
RLDATn
(n=4-1)
91
81
71
63
I
RNEGn/
RLBPVn/
RFSn
(n=4-1)
92
82
72
64
I
Type *
Name/Function
TTL Receive Unipolar Positive Signal Input: When control bit RAIL (bit
7 in register X00H) is a 1, the dual unipolar (positive/negative rail)
mode is selected, and the RPOSn pin carries the receive positive rail
input signal. RPOSn is high whenever a positive pulse is received by
the external line interface transceiver.
Receive Line (NRZ) Data Input: When control bit RAIL (bit 7 in reg-
ister X00H) is a 0, the NRZ mode is selected, and the RLDATn pin
carries the receive NRZ data input signal. RLDATn is normally active
high whenever a positive or negative pulse is received by the external
line interface transceiver. When control bit RXNRZP (bit 0 in register
X01H) is a 1, the QT1F-Plus accepts an inverted data signal and
RLDATn is active low.
TTL Receive Unipolar Negative Signal Input: When control bit RAIL
(bit 7 in register X00H) is a 1, the dual unipolar (positive/negative rail)
mode is selected, and the RNEGn pin carries the receive negative
rail input signal. RNEGn is high whenever a negative pulse is
received by the external line interface transceiver.
External Receive Bipolar Violation Indication Input: When control
bit RAIL (bit 7 in register X00H) is a 0 and the fast sync option is not
selected (control bit RXFS, bit 1 in register X06H, is a 0), the
RLBPVn pin provides an input for indications of external bipolar
violations detected in the external line interface transceiver. A high
indicates a bipolar violation, and increments the internal 16-bit coding
violation counter once on a clock cycle. A bipolar violation is clocked
in on rising edges of the receive line clock LRCLKn.
Receive Fast Sync: When control bit RAIL (bit 7 in register X00H) is
a 0 and the fast sync mode is selected (control bit RXFS, bit 1 in reg-
ister X06H, is a 1), this pin is used for a fast sync feature. A pulse on
this pin is interpreted as identifying bit 192 of the last frame of the
multiframe.
* Note: See Input, Output and Input/Output Parameters section for Type definitions, which depend on the value of VDD selected.
- 11 of 156 -
PRELIMINARY TXC-03103C-MB, Ed. 3
October 2004
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet TXC-03103C.PDF ] | |
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