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PDF PLL701-10 Data sheet ( Hoja de datos )
| Número de pieza | PLL701-10 | |
| Descripción | Low EMI Spread Spectrum Multiplier IC | |
| Fabricantes | PhaseLink | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de PLL701-10 (archivo pdf) en la parte inferior de esta página. Total 8 Páginas | ||
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om PLL701-10Preliminary
.cLow EMI Spread Spectrum Multiplier IC (in Die or Package)
et4UFEATURES
he• Spread Spectrum Clock Generator/Multiplier with
taSoutput selectable from 1x to 8x.
a• 10MHz to 240MHz output with output enable.
.D• 10MHz to 30 MHz reference input frequency
accepted from crystal or external clock signal.
w• Reduced EMI from Spread Spectrum Modulation,
wwith selectable modulation amplitude for Center
w Spread, Down Spread or Asymmetric Spread.
m• TTL/CMOS compatible outputs.
o• 3.3V Operating Voltage.
• 100 ps maximum cycle-to-cycle jitter.
.c• Available in 16-Pin 150mil SSOP or DIE.
DESCRIPTIONS
t4UThe PLL701-10 is a low EMI Clock Generator and
Multiplier for high-speed digital systems. It uses
Spread Spectrum Technology (SST) and permits
edifferent levels of EMI reduction by selecting the
eamplitude of the applied SST. The SST feature can
be turned off. An output enable input is also used.
hThe chip operates with input frequencies ranging from
10 to 30 MHz and provides 1x to 8x at its output.
taSOUTPUT CLOCK (FOUT) SELECTION
aM2
M1
M0
FIN/XIN
(MHz)
Multiplier
FOUT
(MHz)
000
X1 10 ~ 30
.D0 0 1
X2 20 ~ 60
010
X3 30 ~ 90
w0
1
1
0
1
0
10 ~ 30
X4
X5
40 ~ 120
50 ~ 150
w1 0 1
X6 60 ~ 180
110
X7 70 ~ 210
w m1 1 1
X8 80 ~ 240
.coBLOCK DIAGRAM
t4UXIN
eeXOUT
XTAL
OSC
PLL
SST
VDD
FOUT
taShM(0:2)
Control
Logic
PACKAGE PIN CONFIGURATION
XIN/FIN
XOUT/SD0*^
M2^
M1^
M0^
SC0^
SC1^
SC2^
1
2
3
4
5
6
7
8
16 GND
15 AVDD
14 REF/SD1*^
13 VDD
12 SC3^
11 OE^
10 FOUT
9 GND
XIN/FIN = 10 ~ 30 MHz
DIE PAD CONFIGURATION
XOUT/SD0*^
GNDOSC
M2^
M1^
M0^
SC0^
SC1^
AVDD
AVDD
REF/SD1*^
VDD
VDD (optional)
VDD (optional)
SC3^
OE^
FOUT
GNDBUF
Note:
^: Internal pull-up resistor (120kΩ for SD0, 30 kΩ for SC0-
SC2, SD1, M0-M2 and OE). The internal pull-up resistor
results in a default high value when no pull-down resistor is
connected to this pin.
*: SD0 and SD1 are latched upon power-up.
www.Da47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 11/04/02 Page 1
1 page  
Preliminary PLL701-10
Low EMI Spread Spectrum Multiplier IC (in Die or Package)
ELECTRICAL SPECIFICATIONS
1. Absolute Maximum Ratings
PARAMETERS
SYMBOL
MIN.
MAX.
UNITS
Supply Voltage
Input Voltage Range
Output Voltage Range
Soldering Temperature
Storage Temperature
Ambient Operating Temperature*
VDD VSS-0.5
6
V
VI
VSS-0.5
VDD+0.5
V
VO
VSS-0.5
VDD+0.5
V
260 °C
TS -65 150 °C
TA -40 85 °C
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the
device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other
conditions above the operational limits noted in this specification is not implied.
* Note: Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDUSTRIAL), but tested for INDUSTRIAL grade only.
2. DC/AC Specification
PARAMETERS
SYMBOL
CONDITIONS
MIN. TYP. MAX. UNITS
Supply Voltage
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Output High Voltage
Output Low Voltage
Input Frequency
Maximum interruption of FIN
Load Capacitance
Pull-up Resistor
Pull-up Resistor
Short Circuit Current
3.3V Dynamic Supply Current
VDD 3.15 3.45 V
VIH
0.7*VDD
V
VIL
0.3*VDD
V
IIH 100 µA
IIL 100 µA
VOH IOH=5mA, VDD=3.3V 2.4
VOL IOL=6mA, VDD=3.3V
0.4
FXIN When using a crystal 15
30 MHz
FIN When using reference clock 15
30 MHz
When using reference clock
100 µs
CL
Between Pin XIN and
XOUT*
18
pF
Rup PIN 2
120 kΩ
Rup PIN 3,4,5,6,7,8,11,12 30 kΩ
Isc 25 mA
ICC No Load
20 mA
*Note: Pin XIN and XOUT each has a 36pF capacitance. When used with a XTAL, the two capacitors combined load the crystal with 18pF. If driving XIN
with a reference clock signal, the load capacitance will be 36pF (typical).
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 11/04/02 Page 5
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet PLL701-10.PDF ] | |
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