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WJLXT971A Schematic ( PDF Datasheet ) - Intel

Teilenummer WJLXT971A
Beschreibung Single-Port 10/100 Mbps PHY Transceiver
Hersteller Intel
Logo Intel Logo 




Gesamt 30 Seiten
WJLXT971A Datasheet, Funktion
U.com®
taShIPenHetteY4l TrLaXnTs9c7e1ivAerSingle-Port 10/100 MbpsDatasheet
.Da The Intel® LXT971A Single-Port 10/100 Mbps PHY Transceiver (called hereafter the LXT971A
w Transceiver) directly supports both 100BASE-TX and 10BASE-T applications. It provides a
w Media Independent Interface (MII) for easy attachment to 10/100 Media Access Controllers
(MACs). The LXT971A Transceiver is IEEE compliant, and provides a Low Voltage Positive
w Emitter Coupled Logic (LVPECL) interface for use with 100BASE-FX fiber networks. (This
mdocument also supports the Intel® LXT971 Transceiver.) The LXT971A Transceiver supports
full-duplex operation at 10 Mbps and 100 Mbps. Operating conditions for the LXT971A
oTransceiver can be set using auto-negotiation, parallel detection, or manual control. The
LXT971A Transceiver is fabricated with an advanced CMOS process and requires only a single
.c2.53.3 V power supply.
UApplications
t4Combination 10BASE-T/100BASE-TX or
100BASE-FX Network Interface Cards
(NICs)
eNetwork printers
10/100 Personal Computer Memory Card
International Association (PCMCIA) cards
Cable Modems and Set-Top Boxes
eProduct Features
h3.3 V Operation
Low power consumption (300 mW typical)
SLow-power “Sleep” mode
ta10BASE-T and 100BASE-TX using a
single RJ-45 connection
IEEE 802.3-compliant 10BASE-T or
a100BASE-TX ports with integrated filters
Auto-negotiation and parallel detection
.DMII interface with extended register
capability
www .comRobust baseline wander correction
Carrier Sense Multiple Access / Collision
Detection (CSMA/CD) or full-duplex
operation
JTAG boundary scan
MDIO serial port or hardware pin
configurable
100BASE-FX fiber-optic capable
Integrated, programmable LED drivers
— 64-ball Plastic Ball Grid Array (PBGA)
or 64-pin Quad Flat Package (LQFP)
— LXT971ABC - Commercial (0° to 70
°C ambient).
— LXT971ABE - Extended (-40° to
85 °C ambient).
— LXT971ALC - Commercial (0° to
70 °C ambient).
— LXT971ALE - Extended (-40° to
85 °C ambient).
.DataSheet4UDocument Number: 249414-003
www Revision Date: 25-Oct-2005






WJLXT971A Datasheet, Funktion
Intel® LXT971A Single-Port 10/100 Mbps PHY Transceiver
48 Sample Pb-Free (RoHS Compliant) TPBGA Package -
Intel® LXT971A Transceiver.............................................................................. 108
49 Order Matrix for Intel® LXT971A Transceiver - Sample ................................... 110
Tables
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Related Documents from Intel............................................................................. 11
Intel® LXT971A Transceiver LQFP Numeric Pin List .......................................... 15
Intel® LXT971A Transceiver Signal Types.......................................................... 17
Intel® LXT971A Transceiver MII Data Interface Signal Descriptions .................. 18
Intel® LXT971A Transceiver MII Controller Interface Signal Descriptions .......... 19
Intel® LXT971A Transceiver Network Interface Signal Descriptions................... 20
Intel® LXT971A Transceiver Standard Bus and Interface Signal Descriptions ... 20
Intel® LXT971A Transceiver Configuration and LED Driver Signal Descriptions 21
Intel® LXT971A Transceiver Power, Ground, No-Connect Signal Descriptions.. 22
Intel® LXT971A Transceiver JTAG Test Signal Descriptions.............................. 22
Intel® LXT971A Transceiver Pin Types and Modes ............................................ 23
Hardware Configuration Settings for Intel® LXT971A Transceiver ..................... 37
Carrier Sense, Loopback, and Collision Conditions ............................................ 44
4B/5B Coding ...................................................................................................... 51
Valid JTAG Instructions....................................................................................... 60
BSR Mode of Operation ...................................................................................... 61
Device ID Register for Intel® LXT971A Transceiver ........................................... 61
Magnetics Requirements .................................................................................... 62
I/O Pin Comparison of NIC and Switch RJ-45 Setups ........................................ 62
Absolute Maximum Ratings for Intel® LXT971A Transceiver ............................. 70
Recommended Operating Conditions for Intel® LXT971A Transceiver .............. 70
Digital I/O Characteristics (Except for MII, XI/XO, and LED/CFG Pins) .............. 72
Digital I/O Characteristics1 - MII Pins .................................................................. 72
I/O Characteristics - REFCLK/XI and XO Pins.................................................... 73
I/O Characteristics - LED/CFG Pins .................................................................... 73
I/O Characteristics – SD/TP_L Pin ...................................................................... 73
100BASE-TX Transceiver Characteristics .......................................................... 74
100BASE-FX Transceiver Characteristics .......................................................... 74
10BASE-T Transceiver Characteristics............................................................... 74
10BASE-T Link Integrity Timing Characteristics ................................................. 75
Intel® LXT971A Transceiver Thermal Characteristics......................................... 75
Intel® LXT971A Transceiver 100BASE-TX Receive Timing Parameters - 4B Mode
76
Intel® LXT971A Transceiver 100BASE-TX Transmit Timing Parameters - 4B Mode
77
Intel® LXT971A Transceiver 100BASE-FX Receive Timing Parameters ............ 78
Intel® LXT971A Transceiver 100BASE-FX Transmit Timing Parameters ........... 79
Intel® LXT971A Transceiver 10BASE-T Receive Timing Parameters ................ 80
Intel® LXT971A Transceiver 10BASE-T Transmit Timing Parameters ............... 81
Intel® LXT971A Transceiver 10BASE-T Jabber and Unjabber Timing ............... 82
Intel® LXT971A Transceiver 10BASE-T SQE (Heartbeat) Timing ...................... 83
Intel® LXT971A Transceiver Auto-Negotiation and Fast Link Pulse Timing Param-
eters84
6 Datasheet
Document Number: 249414-003
Revision Date: 25-Oct-2005

6 Page









WJLXT971A pdf, datenblatt
Intel® LXT971A Single-Port 10/100 Mbps PHY Transceiver
2.0 Block Diagram for Intel® LXT971A Transceiver
Figure 1 is a block diagram of the LXT971A Transceiver.
Figure 1. Intel® LXT971A Transceiver Block Diagram
RESET_L
ADDR[4:0]
MDIO
MDC
MDINT_L
MDDIS
TX_EN
TXD[3:0]
TX_ER
TX_CLK
LED3/CFG3
LED2/CFG2
LED1/CFG1
COL
RX_CLK
RXD[3:0]
RXDV
CRS
RX_ER
Management /
Mode Select
Logic
Register Set
Clock
Generator
Power Supply
Parallel/Serial
Converter
Manchester
Encoder
10
Scrambler 100
& Encoder
Register
Set
Auto
Negotiation
OSP
Pulse
Shaper
Collision
Detect
Clock
Generator
Media
Select
Serial-to-
Parallel
Carrier Sense Converter
Data Valid
Error Detect
Manchester
10 Decoder
100
Decoder &
Descrambler
OSP
Slicer
+
TP
Driver
-
+
ECL
Driver
-
TP/Fiber
Out
OSP
Adaptive EQ with
Baseline Wander
Cancellation
JTAG
+
100TX
-
+
100FX
-
+
10BT
-
TP/Fiber In
VCC
GND
PWRDWN
REFCLK
TxSLEW[1:0]
TPFOP
TPFON
TDIO
5 TMS
TCK
TRST_L
TPFIP
TPFIN
SD/TP_L
B3386-03
12 Datasheet
Document Number: 249414-003
Revision Date: June 18, 2004

12 Page





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