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WJLXT972A Schematic ( PDF Datasheet ) - Intel

Teilenummer WJLXT972A
Beschreibung Single-Port 10/100 Mbps PHY Transceiver
Hersteller Intel
Logo Intel Logo 




Gesamt 30 Seiten
WJLXT972A Datasheet, Funktion
U.com®
taShIPenHetteY4l TLraXnTs9c7e2iAveSr ingle-Port 10/100 MbpsDatasheet
.Da The Intel® LXT972A Single-Port 10/100 Mbps PHY Transceiver (called hereafter the
w LXT972A Transceiver) directly supports both 100BASE-TX and 10BASE-T applications. The
w LXT972A Transceiver is IEEE compliant and provides a Media Independent Interface (MII) for
easy attachment to 10/100 Media Access Controllers (MACs). The LXT972A Transceiver
w supports full-duplex operation at 10 Mbps and 100 Mbps. Operating conditions for the
mLXT972A Transceiver can be set using auto-negotiation, parallel detection, or manual control.
The LXT972A Transceiver is fabricated with an advanced CMOS process and requires only a
osingle 2.53.3 V power supply with 2.5 V MII interface support.
.cApplications
Combination 10BASE-T/100BASE-TX
UNetwork Interface Cards (NICs)
Network printers
10/100 Personal Computer Memory Card
International Association (PCMCIA) cards
Cable Modems and Set-Top Boxes
t4Product Features
e3.3 V Operation
eLow power consumption (300 mW typical)
h10BASE-T and 100BASE-TX using a
single RJ-45 connection
IEEE 802.3-compliant 10BASE-T or
S100BASE-TX ports with integrated filters
taAuto-negotiation and parallel detection
MII interface with extended register
capability
aRobust baseline wander correction
Carrier Sense Multiple Access / Collision
Detection (CSMA/CD) or full-duplex
operation
JTAG boundary scan
MDIO serial port or hardware pin
configurable
Integrated, programmable LED drivers
64-Pin Low-profile Quad Flat Package
(LQFP)
— LXT972ALC - Commercial (0° to 70 °C
ambient)
www.D .DataSheet4U.comDocument Number: 249186-004
www Revision Date: 25-Oct-2005






WJLXT972A Datasheet, Funktion
Intel® LXT972A Single-Port 10/100 Mbps PHY Transceiver
4 Intel® LXT972A Transceiver MII Data Interface Signal Descriptions .................. 17
5 Intel® LXT972A Transceiver MII Controller Interface Signal Descriptions .......... 18
6 Intel® LXT972A Transceiver Network Interface Signal Descriptions................... 19
7 Intel® LXT972A Transceiver Standard Bus and Interface Signal Descriptions ... 19
8 Intel® LXT972A Transceiver Configuration and LED Driver Signal Descriptions 20
9 Intel® LXT972A Transceiver Power, Ground, No-Connect Signal Descriptions.. 21
10 Intel® LXT972A Transceiver JTAG Test Signal Descriptions.............................. 21
11 Intel® LXT972A Transceiver Pin Types and Modes ............................................ 22
12 Hardware Configuration Settings for Intel® LXT972A Transceiver ..................... 35
13 Carrier Sense, Loopback, and Collision Conditions ............................................ 41
14 4B/5B Coding ...................................................................................................... 48
15 Valid JTAG Instructions....................................................................................... 57
16 BSR Mode of Operation ...................................................................................... 58
17 Device ID Register for Intel® LXT972A Transceiver ........................................... 58
18 Magnetics Requirements .................................................................................... 59
19 I/O Pin Comparison of NIC and Switch RJ-45 Setups ........................................ 59
20 Absolute Maximum Ratings for Intel® LXT972A Transceiver ............................. 63
21 Recommended Operating Conditions for Intel® LXT972A Transceiver .............. 63
22 Digital I/O Characteristics (Except for MII, XI/XO, and LED/CFG Pins) .............. 64
23 Digital I/O Characteristics1 - MII Pins .................................................................. 64
24 I/O Characteristics - REFCLK/XI and XO Pins.................................................... 65
25 I/O Characteristics - LED/CFG Pins .................................................................... 65
26 100BASE-TX Transceiver Characteristics .......................................................... 66
27 10BASE-T Transceiver Characteristics............................................................... 66
28 10BASE-T Link Integrity Timing Characteristics ................................................. 66
29 Intel® LXT972A Transceiver Thermal Characteristics......................................... 67
30 Intel® LXT972A Transceiver 100BASE-TX Receive Timing Parameters ............ 68
31 Intel® LXT972A Transceiver 100BASE-TX Transmit Timing Parameters ........... 69
32 Intel® LXT972A Transceiver 10BASE-T Receive Timing .................................... 70
33 Intel® LXT972A Transceiver 10BASE-T Transmit Timing Parameters ............... 71
34 Intel® LXT972A Transceiver 10BASE-T Jabber and Unjabber Timing ............... 72
35 Intel® LXT972A Transceiver 10BASE-T SQE (Heartbeat) Timing ...................... 73
36 Intel® LXT972A Transceiver Auto-Negotiation / Fast Link Pulse Timing ............ 74
37 Intel® LXT972A Transceiver MDIO Timing ......................................................... 75
38 Intel® LXT972A Transceiver Power-Up Timing................................................... 76
39 Intel® LXT972A Transceiver RESET_L Pulse Width and Recovery Timing........ 77
40 Register Set for IEEE Base Registers................................................................. 78
41 Control Register - Address 0, Hex 0 ................................................................... 79
42 MII Status Register #1 - Address 1, Hex 1 .......................................................... 80
43 PHY Identification Register 1 - Address 2, Hex 2 ............................................... 81
44 PHY Identification Register 2 - Address 3, Hex 3 ............................................... 81
45 Auto-Negotiation Advertisement Register - Address 4, Hex 4 ............................ 82
46 Auto-Negotiation Link Partner Base Page Ability Register - Address 5, Hex 5... 83
47 Auto-Negotiation Expansion - Address 6, Hex 6 ................................................. 84
48 Auto-Negotiation Next Page Transmit Register - Address 7, Hex 7 ................... 85
49 Auto-Negotiation Link Partner Next Page Receive Register - Address 8, Hex 8 85
50 Register Set for Product-Specific Registers ........................................................ 86
51 Configuration Register - Address 16, Hex 10...................................................... 87
52 Status Register #2 - Address 17, Hex 11 ............................................................ 88
53 Interrupt Enable Register - Address 18, Hex 12 ................................................. 89
6 Datasheet
Document Number: 249186-004
Revision Date: 25-Oct-2005

6 Page









WJLXT972A pdf, datenblatt
Intel® LXT972A Single-Port 10/100 Mbps PHY Transceiver
2.0 Block Diagram for Intel® LXT972A Transceiver
Figure 1 is a block diagram of the LXT972A Transceiver.
The LXT972A Transceiver has on-board blocks from Optimal Signal Processing™ (OSP™).
Figure 1. Intel® LXT972A Transceiver Block Diagram
RESET_L
ADDR[4:0]
MDIO
MDC
MDINT_L
MDDIS
TX_EN
TXD[3:0]
TX_ER
TX_CLK
LED3/CFG3
LED2/CFG2
LED1/CFG1
COL
RX_CLK
RXD[3:0]
RXDV
CRS
RX_ER
Management /
Mode Select
Logic
Register Set
Clock
Generator
Power Supply
Parallel/Serial
Converter
Manchester
Encoder
10
Scrambler 100
& Encoder
Register
Set
Auto
Negotiation
OSP
Pulse
Shaper
Collision
Detect
Clock
Generator
Media
Select
Carrier Sense
Data Valid
Error Detect
Serial-to-
Parallel
Converter
Manchester
10 Decoder
100
Decoder &
Descrambler
OSP
Slicer
+
TP
Driver
-
+
ECL
Driver
-
TP Out
OSP
Adaptive EQ with
Baseline Wander
Cancellation
+
100TX
-
JTAG
TP In
+
10BT
-
VCC
GND
PWRDWN
REFCLK
TxSLEW[1:0]
TPOP
TPON
TDIO
5 TMS
TCK
TRST_L
TPIP
TPIN
B3493-02
12 Datasheet
Document Number: 249186-004
Revision Date: 25-Oct-2005

12 Page





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