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WJLXT972M Schematic ( PDF Datasheet ) - Intel

Teilenummer WJLXT972M
Beschreibung Single-Port 10/100 Mbps PHY Transceiver
Hersteller Intel
Logo Intel Logo 




Gesamt 30 Seiten
WJLXT972M Datasheet, Funktion
.DataShIPenHetteY4lU®T.cLraoXmnTs9c7e2ivMerSingle-Port 10/100DaMtabshpesetThe Intel® LXT972M Single-Port 10/100 Mbps PHY Transceiver is an IEEE compliant Fast
Ethernet PHY Transceiver that directly supports both 100BASE-TX and 10BASE-T applications. It
w provides a Media Independent Interface (MII) for easy attachment to 10/100 Media Access
w Controllers (MACs). Both full and half-duplex operation at 10 Mbps and 100 Mbps is supported.
w Operation mode can be set to auto-negotiation, parallel detection, or manual control. The device is
powered from a single 3.3V power supply.
Applications omCombination 10BASE-T/100BASE-TX
.cNetwork Interface Cards (NICs)
Wireless access points
Network printers
10/100 Personal Computer Memory Card
International Association (PCMCIA) cards
Cable Modems and Set-Top Boxes
Product Features t4U3.3V Operation
IEEE 802.3-compliant 10BASE-T or
e100BASE-TX with integrated filters
Auto-negotiation and parallel detection
eMII interface with extended register
capability
hRobust baseline wander correction
Carrier Sense Multiple Access / Collision
Detection (CSMA/CD) or full-duplex
operation
JTAG boundary scan
MDIO serial port or hardware pin
configurable
Integrated, programmable LED drivers
48-pin Low-profile Quad Flat Package
taSRESET_L
ADDR[1:0]
aMDIO
MDC
.DTX_EN
TXD[3:0]
TX_CLK
wLED/CFG[3:1]
wCOL
mRX_CLK
w oRXD[3:0]
.cRX_DV
CRS
t4URX_ER
Management /
Mode Select
Logic
Register Set
Clock
Generator
Power Supply
Parallel/Serial
Converter
Manchester
Encoder
10
Scrambler 100
& Encoder
Register
Set
Auto
Negotiation
OSP
Pulse
Shaper
+
TP
Driver -
TP Out
JTAG
Collision
Detect
Clock
Generator
Carrier Sense
Data Valid
Error Detect
Serial-to-
Parallel
Converter
Manchester
10 Decoder
100
Decoder &
Descrambler
Media
Select
OSP
Slicer
OSP
Adaptive EQ with
Baseline Wander
Cancellation
+
100TX
-
+
10BT
-
TP In
VCC
GND
REFCLK/XI
XO
TPOP
TPON
TDI
5 TDO
TMS
TCK
TRST_L
TPIP
TPIN
B3387-13
.DataSheeDocument Number: 302875-004
wwwRevision Date: February 18, 2005






WJLXT972M Datasheet, Funktion
Intel® LXT972M Single-Port 10/100 Mbps PHY Transceiver
Tables
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47
48
49
Related Documents from Intel............................................................................. 13
Intel® LXT972M Transceiver Signal Types ......................................................... 16
Intel® LXT972M Transceiver LQFP Numeric Pin List ......................................... 16
Intel® LXT972M Transceiver MII Data Interface Signal Descriptions.................. 19
Intel® LXT972M Transceiver MII Controller Interface Signal Descriptions.......... 20
Intel® LXT972M Transceiver Network Interface Signal Descriptions .................. 20
Intel® LXT972M Transceiver Standard Bus and Interface Signal Descriptions .. 20
Intel® LXT972M Transceiver Configuration and LED Driver Signal Descriptions21
Intel® LXT972M Transceiver Power, Ground, No-Connect Signal Descriptions. 22
Intel® LXT972M Transceiver JTAG Test Signal Descriptions ............................. 22
Intel® LXT972M Transceiver Pin Types and Modes ........................................... 23
Intel® LXT972M Transceiver - PHY Device Address Selections......................... 29
Hardware Configuration Settings for Intel® LXT972M Transceiver ..................... 36
Carrier Sense, Loopback, and Collision Conditions ............................................ 42
4B/5B Coding ...................................................................................................... 49
Valid JTAG Instructions....................................................................................... 58
BSR Mode of Operation ...................................................................................... 59
Device ID Register for Intel® LXT972M Transceiver ........................................... 59
Magnetics Requirements .................................................................................... 60
I/O Pin Comparison of NIC and Switch RJ-45 Setups ........................................ 60
Absolute Maximum Ratings for Intel® LXT972M Transceiver ............................. 64
Recommended Operating Conditions for Intel® LXT972M Transceiver.............. 64
Digital I/O Characteristics (Except for MII, XI/XO, and LED/CFG Pins) .............. 65
Digital I/O Characteristics1 - MII Pins .................................................................. 65
I/O Characteristics - REFCLK/XI and XO Pins.................................................... 66
I/O Characteristics - LED/CFG Pins .................................................................... 66
100BASE-TX Transceiver Characteristics .......................................................... 67
10BASE-T Transceiver Characteristics............................................................... 67
10BASE-T Link Integrity Timing Characteristics ................................................. 67
Intel® LXT972M Transceiver 100BASE-TX Receive Timing Parameters ........... 68
Intel® LXT972M Transceiver 100BASE-TX Transmit Timing Parameters ......... 69
Intel® LXT972M Transceiver 10BASE-T Receive Timing ................................... 70
Intel® LXT972M Transceiver 10BASE-T Transmit Timing .................................. 71
Intel® LXT972M Transceiver 10BASE-T Jabber and Unjabber Timing............... 72
Intel® LXT972M Transceiver 10BASE-T SQE (Heartbeat) Timing ..................... 73
Intel® LXT972M Transceiver Auto-Negotiation / Fast Link Pulse Timing ............ 74
Intel® LXT972M Transceiver MDIO Timing ......................................................... 75
Intel® LXT972M Transceiver Power-Up Timing .................................................. 76
Intel® LXT972M Transceiver RESET_L Pulse Width and Recovery Timing ....... 77
Register Set for IEEE Base Registers................................................................. 78
Control Register - Address 0, Hex 0 ................................................................... 79
MII Status Register #1 - Address 1, Hex 1 .......................................................... 80
PHY Identification Register 1 - Address 2, Hex 2 ............................................... 81
PHY Identification Register 2 - Address 3, Hex 3 ............................................... 81
Auto-Negotiation Advertisement Register - Address 4, Hex 4 ............................ 82
Auto-Negotiation Link Partner Base Page Ability Register - Address 5, Hex 5... 83
Auto-Negotiation Expansion - Address 6, Hex 6 ................................................. 84
Auto-Negotiation Next Page Transmit Register - Address 7, Hex 7 ................... 85
Auto-Negotiation Link Partner Next Page Receive Register - Address 8, Hex 8 85
6 Datasheet
Document Number: 302875-004
Revision Date: 27-Oct-2005

6 Page









WJLXT972M pdf, datenblatt
Intel® LXT972M Single-Port 10/100 Mbps PHY Transceiver
2.0 Block Diagram for Intel® LXT972M Transceiver
Figure 1 is a block diagram of the LXT972M Transceiver. (This block diagram is the same as the
block diagram on the first page of this document. This copy of the block diagram appears here as a
convenience to the reader.)
Figure 1. Intel® LXT972M Transceiver Block Diagram
RESET_L
ADDR[1:0]
MDIO
MDC
TX_EN
TXD[3:0]
TX_CLK
LED/CFG[3:1]
COL
RX_CLK
RXD[3:0]
RX_DV
CRS
RX_ER
Management /
Mode Select
Logic
Register Set
Clock
Generator
Power Supply
Parallel/Serial
Converter
Manchester
Encoder
10
Scrambler 100
& Encoder
Register
Set
Auto
Negotiation
OSP
Pulse
Shaper
+
TP
Driver -
TP Out
JTAG
Collision
Detect
Clock
Generator
Serial-to-
Parallel
Carrier Sense Converter
Data Valid
Error Detect
Manchester
10 Decoder
100
Decoder &
Descrambler
Media
Select
OSP
Slicer
OSP
Adaptive EQ with
Baseline Wander
Cancellation
+
100TX
-
+
10BT
-
TP In
VCC
GND
REFCLK/XI
XO
TPOP
TPON
TDI
5 TDO
TMS
TCK
TRST_L
TPIP
TPIN
B3387-13
14 Datasheet
Document Number: 302875-005
Revision Date: 27-Oct-2005

12 Page





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