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S3076 Schematic ( PDF Datasheet ) - Applied Micro Circuits

Teilenummer S3076
Beschreibung Multi-Rate Sonet/SDH Clock Recovery Unit
Hersteller Applied Micro Circuits
Logo Applied Micro Circuits Logo 




Gesamt 18 Seiten
S3076 Datasheet, Funktion
®
mDEVICE
.coSMPEUCLITFIIC-RATAIOTEN SONET/SDH CLOCK RECOVERY UNIT
BMiUCLMTOI-SRAPTEECLSOCNLEOTC/KSDGHECNLEORCAKTORRECOVERY UNIT
S3076
S3076
et4UFEATURES
he• SiGe BiCMOS technology
S• Complies with Bellcore and ITU-T specifica-
tations for jitter tolerance, jitter transfer and
ajitter generation
.D• On-chip high frequency PLL with internal
w loop filter for clock recovery
w • Supports clock recovery for:
w OC-48 (2488.32 Mbps) (with FEC)
Fibre Channel (2125 Mbps) (with FEC)
mOC-24 (1244.16 Mbps) (with FEC)
Gigabit Ethernet (1250 Mbps) (with FEC)
oFibre Channel (1062.5 Mbps) (with FEC)
.cOC-12 (622.08 Mbps) (with FEC)
OC-3 (155.52 Mbps) (with FEC) NRZ data
• Selectable reference frequencies
U19.44 MHz or 155.52 MHz
(or equivalent Fibre Channel/
t4Gigabit Ethernet frequencies)
• Lock detect—monitors frequency of
eincoming data
e• Low-jitter serial interface
• +3.3 V supply
h• Compact 48 pin TQFP TEP package
S• Typical power 620 mW
• Available in Die form also
GENERAL DESCRIPTION
The function of the S3076 clock recovery unit is to
derive high speed timing signals for SONET/SDH-
based equipment. The S3076 is implemented using
AMCC’s proven Phase Locked Loop (PLL) technology.
Figure 1 shows a typical network application.
The S3076 receives an OC-48, OC-24, OC-12, OC-3,
Fibre Channel or Gigabit Ethernet scrambled NRZ sig-
nal with FEC capability up to 8 bytes per 255-byte
block and recovers the clock from the data. The chip
outputs a differential bit clock and retimed data.
The S3076 utilizes an on-chip PLL which consists
of a phase detector, a loop filter, and a Voltage
Controlled Oscillator (VCO). The phase detector
compares the phase relationship between the VCO
output and the serial data input. A loop filter con-
verts the phase detector output into a smooth DC
voltage, and the DC voltage is input to the VCO
whose frequency is varied by this voltage. A block
diagram is shown in Figure 2.
ataFigure 1. System Block Diagram
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October 23, 2000 / Revision A
1






S3076 Datasheet, Funktion
S3076
MULTI-RATE SONET/SDH CLOCK RECOVERY UNIT
Table 5. Pin Assignment and Descriptions
Pin Name
Level I/O Pin#
Description
SERDATIP
SERDATIN
BYPASS
SDN
REFCLKP
REFCLKN
CAP1
CAP2
LCKREFN
RATESEL0
RATESEL1
TESTCLK
REFSEL
RST
TESTEN
SERDATOP
SERDATON
SERCLKOP
SERCLKON
LOCKDET
Diff.
CML
LVTTL
I
I
Single
Ended
LVPECL
I
Internally
Biased
Diff.
LVPECL
I
I
LVTTL
I
LVTTL
I
LVTTL
LVTTL
LVTTL
I
I
I
LVTTL
I
Diff.
CML
Diff.
CML
O
O
LVTTL O
3 Serial Data In. Clock is recovered from the transitions on these
2 inputs. Internally biased and terminated. (See Figure 10.)
46
Active High. Used to bypass the PLL. It allows transmission of data
input without clock recovery.
Signal Detect. Active Low. A single-ended 10K PECL input to be
driven by the external optical receiver module to indicate a loss of
45
received optical power. When SDN is inactive, the data on the Serial
Data In (SERDATIP/N) pins will be internally forced to a constant zero,
and the PLL will be forced to lock to the REFCLK inputs. When SDN
is active, data on the SERDATIP/N pins will be processed normally.
Reference Clock. 155.52/19.44 MHz (or equivalent Fibre Channel
6
7
or Gigabit Ethernet frequency) input used to establish the initial
operating frequency of the clock recovery PLL and also used as a
standby clock in the absence of data, during reset or when SDN is
inactive. Internally biased.
40 Loop Filter Capacitor. The external loop filter capacitor and resistors
39 are connected to these pins. (See Figure 14.)
17
Lock to Reference. Active Low. When active, the serial clock output
will be forced to lock to the local reference clock input [REFCLK].
20
19
Rate Select. Selects the operating mode (See Table 1.)
15
Test Clock. Test input signal used for production test. Connect to
Ground for normal operation. This input is internally pulled High.
18 Selects the reference frequency (See Table 2.)
16
Reset Input. Active High. Resets lock detect circuit and VCO divide-
by-N circuit for production test.
Test Enable. Active High. Bypasses the VCO for production test.
47 Connect to Ground for normal operation. This input is internally
pulled High.
28
27
Serial Data Out. This signal is the delayed version of the incoming
data stream (SERDATIP/N) updated on the falling edge of Serial
Clock Out (SERCLKOP/N).
34 Serial Clock Out. This signal is phase aligned with Serial Data Out
33 (SERDATO). (See Figure 8.)
Lock Detect. Clock recovery indicator. Set high when the internal
10 clock recovery has locked onto the incoming data stream.
LOCKDET is an asynchronous output.
6 October 23, 2000 / Revision A

6 Page









S3076 pdf, datenblatt
S3076
MULTI-RATE SONET/SDH CLOCK RECOVERY UNIT
Figure 8. Receiver Output Timing Diagram
SERCLKOP
SERDATOP/N
50%
tSU tH
Note: Output propagation delay time of high speed CML outputs is the time in pico seconds from the cross-over point of the
reference signal to the cross-over point of the output.
Table 8. Jitter Tolerance Specifications
Parameter
Min Typ Max Units Conditions
Jitter Tolerance
STS-48
0.4 0.5
UI
1 MHz < f < 5 MHz
Data Pattern = 27-1 PRBS
Jitter Tolerance
STS-24
Jitter Tolerance
STS-12
0.4 0.6
UI
250 kHz < f < 5 MHz
Data Pattern = 27-1 PRBS
Jitter Tolerance
STS-3
0.4 0.8
UI
65 kHz < f < 1 MHz
Data Pattern = 27-1 PRBS
Table 9. Gigabit Ethernet Jitter Specifications
Parameter
Min Typ Max Units Conditions
t Total Input Jitter Tolerance
J
tDJ Deterministic Input Jitter
Tolerance
599
370
ps As specified in IEEE 802.3z.
ps As specified in IEEE 802.3z.
12 October 23, 2000 / Revision A

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