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DM74LS74A Schematic ( PDF Datasheet ) - Fairchild Semiconductor

Teilenummer DM74LS74A
Beschreibung Dual Positive-Edge-Triggered D Flip-Flops
Hersteller Fairchild Semiconductor
Logo Fairchild Semiconductor Logo 




Gesamt 6 Seiten
DM74LS74A Datasheet, Funktion
August 1986
Revised March 2000
DM74LS74A
Dual Positive-Edge-Triggered D Flip-Flops with
Preset, Clear and Complementary Outputs
General Description
This device contains two independent positive-edge-trig-
gered D flip-flops with complementary outputs. The infor-
mation on the D input is accepted by the flip-flops on the
positive going edge of the clock pulse. The triggering
occurs at a voltage level and is not directly related to the
transition time of the rising edge of the clock. The data on
the D input may be changed while the clock is LOW or
HIGH without affecting the outputs as long as the data
setup and hold times are not violated. A low logic level on
the preset or clear inputs will set or reset the outputs
regardless of the logic levels of the other inputs.
Ordering Code:
Order Number Package Number
Package Description
DM74LS74AM
M14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow
DM74LS85ASJ
M14D
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
DM74LS74AN
N14A
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Function Table
Inputs
Outputs
PR CLR CLK D
Q
Q
LHXX
H
L
HLXX
L
H
L L X X H (Note 1) H (Note 1)
HHH
H
L
HHL
L
H
HH L X
Q0
Q0
H = HIGH Logic Level
X = Either LOW or HIGH Logic Level
L = LOW Logic Level
↑ = Positive-going Transition
Q0 = The output logic level of Q before the indicated input conditions were
established.
Note 1: This configuration is nonstable; that is, it will not persist when either
the preset and/or clear inputs return to their inactive (HIGH) level.
© 2000 Fairchild Semiconductor Corporation DS006373
www.fairchildsemi.com






DM74LS74A Datasheet, Funktion
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Package Number N14A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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