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NHI-15391RT Schematic ( PDF Datasheet ) - National Hybrid

Teilenummer NHI-15391RT
Beschreibung (NHI Series) Multi-Protocol Data Bus Interface
Hersteller National Hybrid
Logo National Hybrid Logo 




Gesamt 30 Seiten
NHI-15391RT Datasheet, Funktion
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ww mThe information provided in this document is believed to be accurate; however, no responsibility is assumed by NATIONAL
oHYBRID, INC. for its use, and no license or rights are granted by implication or otherwise in connection therewith. Specifications
.care subject to change without notice.
t4U2200 Smithtown Avenue, Ronkonkoma, NY 11779
eeTelephone (631) 981- 2400 Data Bus Fax (631) 981- 2445
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NHI-15391RT Datasheet, Funktion
3.1.2
REMOTE TERMINAL HIGHLIGHTS:
DBCA_ L bit is controlled in configuration register.
Message Illegality is internally programmable. DOES NOT require external PROMS or glue
logic.
Employs data tables with individual tag words which indicate whether or not the data is valid,
updated since last read, in the process of being updated, was received via broadcast
command, or has been lost (i. e. updated more than once by a receive message before being
read).
Optionally sets the subsystem flag bit whenever stale data is transmitted or received data is
overwritten.
Issues interrupts on any subset of T/ R bit, subaddresses, mode commands, broadcast
messages and errors.
Provides interrupt priority input and output pins for daisy- chaining interrupt requests.
messages.
Optionally resets the real- time clock in response to a "Synchronize" mode command.
Optionally updates the lower 16 bits of the real- time clock in response to a "Synchronize
WithData" command.
Indicates the reception of specific commands by outputting pulses on any one of 8 pins.
Internally loops- back messages under host control for test purposes.
Employs a decoder algorithm which ensures high noise immunity and a low error rate.
Software RT Address Lockout.
MDC3818 Status Response, Error Handling, Status Bit Definition, Mode Code Operation.
Separate Broadcast Interrupts.
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6 Page









NHI-15391RT pdf, datenblatt
INTERNAL REGISTER MAP
ADDRESS
REGISTER DEFINITION
ACCESS
0 CONTROL
1 POINTER TABLE ADDRESS
R/W
R/W
2 BASIC STATUS
3 INTERRUPT MASK(lower byte)
R/W
R/W
3 INTERRUPT VECTOR(upper byte)
R
3 INTERRUPT REQUEST(upper byte)
W
4 INTERRUPT VECTOR(lower byte)
4 AUXILLARY VECTOR(upper byte)
R/W
R
4 RESERVED(upper byte)
W
5 REAL TIME CLOCK HIGH WORD
6 REAL TIME CLOCK LOW WORD
R
R
7 REAL TIME CLOCK CONTROL
8 READ FIFO
R/W
R
8 RESET FIFO
W
9 CONFIGURATION 1
R/W
10 RESERVED
11 LAST COMMAND
R
12 LAST STATUS
13 RESERVED
R
14 RESERVED
15 RESET TERMINAL(both bytes)
W
16 RESERVED
17 RESERVED
18 ENCODER STATUS
19 CONDITION
R
R
20 RESERVED
21 CONFIGURATION 3
R/W
22 RESERVED
23 ENCODER DATA*
24 ENCODER DATA TX REQUEST*
R/W
W
25 ENCODER COMMAND TX REQUEST*
W
26 RESERVED
27 RESERVED
28 RESERVED
29 RESERVED
30 EXTERNAL RTU ADDRESS BUFFER(lowre byte)
R
30 COMMAND OUTPUT PINS
W
31 I/O TAG WORD
R/W
DO NOT WRITE TO RESERVED REGISTERS.
*In order to write to addresses 23, 24, or 25, the RT must be in loop- back mode (see CONTROL
register for details).
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12 Page





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