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PDF MT4LC16M4A7 Data sheet ( Hoja de datos )
| Número de pieza | MT4LC16M4A7 | |
| Descripción | DRAM | |
| Fabricantes | Micron Technology | |
| Logotipo |  |
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DRAM
16 MEG x 4
FPM DRAM
MT4LC16M4A7, MT4LC16M4T8
For the latest data sheet, please refer to the Micron Web
site: www.micronsemi.com/mti/msp/html/datasheet.html
FEATURES
• Single +3.3V ±0.3V power supply
• Industry-standard x4 pinout, timing, functions,
and packages
• 13 row, 11 column addresses (A7)
12 row, 12 column addresses (T8)
• High-performance CMOS silicon-gate process
• All inputs, outputs and clocks are LVTTL-compat-
ible
• FAST-PAGE-MODE (FPM) access
• 4,096-cycle CAS#-BEFORE-RAS# (CBR) REFRESH
distributed across 64ms
• Optional self refresh (S) for low-power data
retention
OPTIONS
• Refresh Addressing
4,096 (4K) rows
8,192 (8K) rows
MARKING
T8
A7
• Plastic Packages
32-pin SOJ (400 mil)
32-pin TSOP (400 mil)
DJ
TG
• Timing
50ns access
60ns access
-5
-6
• Refresh Rates
Standard Refresh
Self Refresh (128ms period)
None
S*
NOTE: 1. The 16 Meg x 4 FPM DRAM base number
differentiates the offerings in one place—
MT4LC16M4A7. The fifth field distinguishes
various options: A7 designates an 8K refresh and
T8 designates a 4K refresh for FPM DRAMs.
2. The # symbol indicates signal is active LOW.
*Contact factory for availability
Part Number Example:
MT4LC16M4A7DJ
KEY TIMING PARAMETERS
SPEED
-5
-6
tRC
90ns
110ns
tRAC
50ns
60ns
tPC
30ns
35ns
tAA
25ns
30ns
tCAC
13ns
15ns
PIN ASSIGNMENT (Top View)
32-Pin SOJ
32-Pin TSOP
VCC
DQ0
DQ1
NC
NC
NC
NC
WE#
RAS#
A0
A1
A2
A3
A4
A5
VCC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32 VSS
31 DQ3
30 DQ2
29 NC
28 NC
VCC
DQ0
DQ1
NC
NC
NC
1
2
3
4
5
6
27 NC
NC 7
26 CAS#
WE# 8
25 OE#
RAS# 9
24
A12/NC**
A0
A1
10
11
23 A11
A2 12
22 A10
A3 13
21 A9
A4 14
20 A8
19 A7
A5 15
VCC 16
18 A6
17 VSS
32 VSS
31 DQ3
30 DQ2
29 NC
28 NC
27 NC
26 CAS#
25 OE#
24 A12/NC**
23 A11
22 A10
21 A9
20 A8
19 A7
18 A6
17 VSS
**A12 on A7 version and NC on T8 version
16 MEG x 4 FPM DRAM PART NUMBERS
PART NUMBER
REFRESH
ADDRESSING PACKAGE REFRESH
MT4LC16M4A7DJ-x
8K
SOJ Standard
MT4LC16M4A7DJ-x S
8K
SOJ Self
MT4LC16M4A7TG-x
8K
TSOP Standard
MT4LC16M4A7TG-x S
8K
TSOP
Self
MT4LC16M4T8DJ-x
4K
SOJ Standard
MT4LC16M4T8DJ-x S
4K
SOJ Self
MT4LC16M4T8TG-x 4K TSOP Standard
MT4LC16M4T8TG-x S
4K
TSOP
Self
x = speed
GENERAL DESCRIPTION
The 16 Meg x 4 DRAMs are high-speed CMOS,
dynamic random-access memory devices contain-ing
67,108,864 bits organized in a x4 configuration. The
MT4LC16M4A7 and MT4LC16M4T8 are functionally
organized as 16,777,216 locations containing four bits
each. The 16,777,216 memory locations are arranged in
8,192 rows by 2,048 columns for the MT4LC16M4A7 or
4,096 rows by 4,096 columns for the MT4LC16M4T8.
During READ or WRITE cycles, each location is uniquely
16 Meg x 4 FPM DRAM
D21_2.p65 – Rev. 5/00
1 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000, Micron Technology, Inc.
1 page  
16 MEG x 4
FPM DRAM
ICC OPERATING CONDITIONS AND MAXIMUM LIMITS
(Notes: 1, 2, 3, 5, 6) (VCC = +3.3V ±0.3V)
PARAMETER/CONDITION
STANDBY CURRENT: TTL
(RAS# = CAS# = VIH)
STANDBY CURRENT: CMOS
(RAS# = CAS# VCC - 0.2V, DQs may be left open,
other inputs: VIN VCC - 0.2V or VIN ≤ 0.2V)
OPERATING CURRENT: Random READ/WRITE
Average power supply current
(RAS#, CAS#, address cycling: tRC = tRC [MIN])
OPERATING CURRENT: FAST PAGE MODE
Average power supply current (RAS# = VIL,
CAS#, address cycling: tPC = tPC [MIN])
REFRESH CURRENT: RAS#-ONLY
Average power supply current
(RAS# cycling, CAS# = VIH: tRC = tRC [MIN])
REFRESH CURRENT: CBR
Average power supply current
(RAS#, CAS#, address cycling: tRC = tRC [MIN])
REFRESH CURRENT: Extended (“S” version only)
Average power supply current: CAS# = 0.2V or
CBR cycling; RAS# = tRAS (MIN); WE# = VCC - 0.2V;
A0-A11, OE# and DIN = VCC - 0.2V or 0.2V
(DIN may be left open)
REFRESH CURRENT: Self (“S” version only)
Average power supply current: CBR with
RAS# tRASS (MIN) and CAS# held LOW;
WE# = VCC - 0.2V; A0-A11, OE# and DIN =
VCC - 0.2V or 0.2V (DIN may be left open)
SYMBOL
ICC1
SPEED
ALL
4K 8K
REFRESH REFRESH UNITS NOTES
1 1 mA
ICC2 ALL 500
ICC3 -5 170
-6 160
ICC4 -5 100
-6 90
ICC5 -5 170
-6 160
ICC6 -5 170
-6 160
500 µA
130 mA 25
120
100 mA 25
90
130 mA 22
120
130 mA 4, 7
120
ICC7 ALL 400
400 µA 4, 7
ICC8 ALL 400
400 µA 4, 7
16 Meg x 4 FPM DRAM
D21_2.p65 – Rev. 5/00
5 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000, Micron Technology, Inc.
5 Page 
RAS# VVIIHL
CAS#
V
V
IH
IL
ADDR
V
V
IH
IL
WE#
V
V
IH
IL
DQ
V
V
IOH
IOL
OE#
V
V
IH
IL
READ-WRITE CYCLE
(LATE WRITE and READ-MODIFY-WRITE cycles)
tRWC
tRAS
tCRP
tRCD
tCSH
tRSH
tCAS
tASR
tAR
tRAD
tRAH
ROW
tASC
tCAH
COLUMN
tRCS
tRWD
tCWD
tAWD
tCWL
tRWL
tWP
tCLZ
OPEN
tAA
tRAC
tCAC
tOE
tDS tDH
VALID D OUT
tOD
VALID D IN
tOEH
16 MEG x 4
FPM DRAM
tRP
ROW
OPEN
DON’T CARE
UNDEFINED
TIMING PARAMETERS
SYMBOL
tAA
tAR
tASC
tASR
tAWD
tCAC
tCAH
tCAS
tCLZ
tCRP
tCSH
tCWD
tCWL
tDH
tDS
MIN
40
0
0
48
8
13
3
5
50
36
13
8
0
-5
MAX
25
13
10,000
MIN
45
0
0
55
10
15
3
5
60
40
15
10
0
-6
MAX
30
15
10,000
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SYMBOL
tOD
tOE
tOEH
tRAC
tRAD
tRAH
tRAS
tRCD
tRCS
tRP
tRSH
tRWC
tRWD
tRWL
tWP
MIN
3
13
13
8
50
18
0
30
13
131
73
13
8
-5
MAX
13
13
50
10,000
MIN
3
15
15
10
60
20
0
40
15
155
85
15
10
-6
MAX
15
15
60
10,000
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
16 Meg x 4 FPM DRAM
D21_2.p65 – Rev. 5/00
11
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000, Micron Technology, Inc.
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet MT4LC16M4A7.PDF ] | |
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