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PDF PLL1708 Data sheet ( Hoja de datos )
| Número de pieza | PLL1708 | |
| Descripción | 3.3 V DUAL PLL MULTICLOCK GENERATOR | |
| Fabricantes | Burr-Brown Corporation | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de PLL1708 (archivo pdf) en la parte inferior de esta página. Total 22 Páginas | ||
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PLL1707
PLL1708
SLES065 – DECEMBER 2002
3.3ĆV DUAL PLL MULTICLOCK GENERATOR
FEATURES
D 27-MHz Master Clock Input
D Generated Audio System Clock (PLL1707):
– SCKO0: 768 fS (fS = 44.1 kHz)
– SCKO1: 768 fS, 512 fS (fS = 48 kHz)
– SCKO2: 256 fS (fS = 32, 44.1, 48, 64, 88.2,
96 kHz)
– SCKO3: 384 fS (fS = 32, 44.1, 48, 64, 88.2,
96 kHz)
D Generated Audio System Clock (PLL1708):
– SCKO0: 768 fS (fS = 44.1 kHz)
– SCKO1: 768 fS, 512 fS, 384 fS, 256 fS
(fS = 48 kHz)
– SCKO2: 256 fS (fS = 16, 22.05, 24, 32, 44.1,
48, 64, 88.2, 96 kHz)
– SCKO3: 384 fS (fS = 16, 22.05, 24, 32, 44.1,
48, 64, 88.2, 96 kHz)
D Zero PPM Error Output Clocks
D Low Clock Jitter: 50 ps (Typical)
D Multiple Sampling Frequencies (PLL1707):
– fS = 32, 44.1, 48, 64, 88.2, 96 kHz
D Multiple Sampling Frequencies (PLL1708):
– fS = 16, 22.05, 24, 32, 44.1, 48, 64, 88.2,
96 kHz
D 3.3-V Single Power Supply
D PLL1707: Parallel Control
PLL1708: Serial Control
D Package: 20-Pin SSOP (150 mil), Lead-Free
Product
APPLICATIONS
D HDD + DVD Recorders
D DVD Recorders
D HDD Recorders
D DVD Players
D DVD Add-On Cards for Multimedia PCs
D Digital HDTV Systems
D Set-Top Boxes
DESCRIPTION
The PLL1707† and PLL1708† are low cost, phase-locked
loop (PLL) multiclock generators. The PLL1707 and
PLL1708 can generate four system clocks from a 27-MHz
reference input frequency. The clock outputs of the
PLL1707 can be controlled by sampling frequency-control
pins and those of the PLL1708 can be controlled through
serial-mode control pins. The device gives customers both
cost and space savings by eliminating external
components and enables customers to achieve the very
low-jitter performance needed for high performance audio
DACs and/or ADCs. The PLL1707 and PLL1708 are ideal
for MPEG-2 applications which use a 27-MHz master
clock such as DVD recorders, HDD recorders, DVD
add-on cards for multimedia PCs, digital HDTV systems,
and set-top boxes.
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate
precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to
damage because very small parametric changes could cause the device not to meet its published specifications.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
†The PLL1707 and PLL1708 use the same die and they are electrically identical except for mode control.
PRODUCTION DATA information is current as of publication date. Products
conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters.
Copyright 2002, Texas Instruments Incorporated
1 page  
www.ti.com
PLL1707 Terminal Functions
TERMINAL
NAME
NO.
I/O
DESCRIPTION
AGND
CSEL
9 – Analog ground
12 I SCKO1 frequency selection control(1)
DGND1 4 – Digital ground 1
DGND2 16 – Digital ground 2
DGND3 17 – Digital ground 3
FS1 5 I Sampling frequency group control 1(1)
FS2 6 I Sampling frequency group control 2(1)
MCKO1 14 O 27-MHz master clock output 1
MCKO2 15 O 27-MHz master clock output 2
SCKO0
18 O System clock output 0 (33.8688 MHz fixed)
SCKO1
19 O System clock output 1 (selectable for 48 kHz)
SCKO2
SCKO3
SR
2 O System clock output 2 (256 fS selectable)
3 O System clock output 3 (384 fS selectable)
7 I Sampling rate control(1)
VCC
VDD1
VDD2
VDD3
XT1
8 – Analog power supply, 3.3 V
1 – Digital power supply 1, 3.3 V
13 – Digital power supply 2, 3.3 V
20 – Digital power supply 3, 3.3 V
10 I 27-MHz crystal oscillator, or external clock input
XT2 11 O 27-MHz crystal oscillator, must be OPEN for external clock input mode
(1) Schmitt-trigger input with internal pulldown.
PLL1707
PLL1708
SLES065 – DECEMBER 2002
5
5 Page 
www.ti.com
Table 2. Sampling Frequencies
SAMPLING RATE
Half sampling frequencies†
Standard sampling frequencies
Double sampling frequencies
† PLL1708 only
SAMPLING FREQUENCY (kHz)
16 22.05 24
32 44.1 48
64 88.2 96
PLL1707
PLL1708
SLES065 – DECEMBER 2002
Table 3. Sampling Frequencies and System Clock Output Frequencies
SAMPLING FREQUENCY (kHz)
16†
22.05†
24†
32
44.1
48
64
88.2
96
† PLL1708 only
SAMPLING RATE
Half
Half
Half
Standard
Standard
Standard
Double
Double
Double
256 fS
384 fS
SCKO2 (MHZ) SCKO3 (MHZ)
4.096
6.144
5.6448
8.4672
6.144
9.216
8.192
12.288
11.2896
16.9344
12.288
18.432
16.384
24.576
22.5792
33.8688
24.576
36.864
Response time from power on (or applying the clock to XT1) to SCKO settling time is typically 3 ms. Delay time from
sampling frequency change to SCKO settling is 300 ns maximum. Figure 10 illustrates SCKO transient timing in the
PLL1708.
MS
SCKO2
SCKO3
Stable
300 ns
1–2 Clocks of MCKO1, 2
Clock Transition Region
Stable
SCKO0
SCKO1
33.8688 , 36.864, or 24.576 MHz
Figure 10. System Clock Transient Timing
The delay time for hardware control to use SR, FS2, FS1, or CSEL is 150 ns maximum. Figure 11 illustrates SCKO transient
timing in the PLL1707. Clock transient timing is not synchronized with the SCKOs. External buffers are recommended on
all output clocks in order to avoid degrading the jitter performance of the PLL1707/8.
11
11 Page | ||
| Páginas | Total 22 Páginas | |
| PDF Descargar | [ Datasheet PLL1708.PDF ] | |
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