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PDF TXC-03401B Data sheet ( Hoja de datos )
| Número de pieza | TXC-03401B | |
| Descripción | DS3F Device DS3 Framer | |
| Fabricantes | Transwitch | |
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DS3F Device
m DS3 Framer
o TXC-03401B
eet4U.cFEATURES
Sh• DS3 payload access, bit-serial or nibble-parallel
ta• C-bit parity or M13 operating mode
.Da• C-bit interface (13 C-bits in, 14 out)
w• Detect and generate DS3 AIS, and idle signals
w• Transmit reference generator for serial operation
w• Transmit and receive Far End Alarm and Control
m(FEAC) with double word capability and automatic
transmission
o• Maskable hardware interrupt for eight alarms
.c• Transmit single errors: framing, FEBE, C-bit parity,
and P-bit parity
U• FEBE, C-bit, and P-bit performance counters
t4• Counters for F-bit and M-bit errors
• Counter for coding violations and excessive zeros
e• Transmit-to-Receive and Receive-to-Transmit
eloopbacks
• Outputs can be set to high-impedance state
h• Selectable mode for TXC-03401 emulation
S• Single +5 volt power supply
ta• Available as 68-pin plastic leaded chip carrier or
80-pin thin plastic quad flat package (TQFP)
DATA SHEET
DESCRIPTION
The DS3F is designed for DS3 framer applications in
which broadband payloads are mapped into the 44.736
Mbit/s DS3 frame format. Although the C-bit parity for-
mat is recommended, the DS3F can also operate in the
M13 mode. In the C-bit parity format, the DS3F provides
a separate interface for selected C-bits. The DS3F also
provides for transmitting and receiving the FEAC chan-
nel and Blue code AIS conditions, and generates and
detects DS3 AIS, DS3 idle, P-bit parity and C-bit parity.
In addition, performance counters are provided, as well
as the ability to generate single framing, FEBE, C-bit
parity and P-bit parity errors. The device also provides
X-bit inversion, receive loop timing and indications for
FEAC idle channel, FEAC word stack overflow and
Severely Errored Frame. The payload interface is select-
able through software as either a bit-serial or nibble-par-
allel format.
APPLICATIONS
• Subrate multiplexing
• Wideband data or video transport
• DS3 monitor and test
• Channel extenders
• DS3 test sets
.DaLINE SIDE
+5V
TERMINAL SIDE
ww mDS3 NRZ I/O
w et4U.coclock & data
DS3F
DS3 Framer
TXC-03401B
Serial/nibble
clock, data &
frame output
Transmit DS3
reference generator
output
Serial/nibble
clock, data &
frame input
heDS3 stuff bits
SMicroprocessor clock & data
C-bits I/O
clocks & data
tainterface
Transmit errors
.DaCopyright 2001 TranSwitch Corporation
wTranSwitch and TXC and are registered trademarks of TranSwitch Corporation
Document Number:
TXC-03401B-MB
Ed. 6, June 2001
wTranSwitch Corporation • 3 Enterprise Drive • Shelton, Connecticut 06484 • USA
wTel: 203-929-8810 • Fax: 203-926-9453 • www.transwitch.com
1 page  
Proprietary TranSwitch Corporation Information for use Solely by its Customers
DATA SHEET
DS3F
TXC-03401B
mode, the C-bits may be generated internally (such as C-bit parity), written by the microprocessor (such as the
FEAC channel), or provided from the external C-bit interface. In C-bit Parity mode, the C1 bit is always trans-
mitted as a 1. The transmit C-bit interface consists of a data input signal (CXD), a clock signal (CXCK), a fram-
ing pulse (CXF) and a data communication link clock (CXDCC). For M13 mode, all of the C-bits are input from
the terminal side’s bit-serial interface. The DS3 transmit line side interface consists of the data signal (D3TD)
and a clock signal (D3TC).
DS3F transmit-to-receive (TR) loopback is controlled by setting a bit in the memory map (3LOOP). The entire
device is used when loopback is in effect, but the line side input data and clock are blocked (by the gate pre-
ceding the DS3 Frame Alignment Block shown in Figure 1). In the Extended-features mode of operation, a
receive-to-transmit payload (RTP) loopback is also available by use of control bit RTPLOOP.
The capability to generate and transmit single overhead bit errors is also provided. External interfaces are pro-
vided for transmitting a far end block error (FORCEFEBE), a P-bit parity error (FORCEPP), a C-bit parity error
(FORCECP) and an overhead bit error (FORCEOE). The FORCEOE signal is used in conjunction with the
enable signal (OENA) for introducing an overhead bit error in the next 85-bit segment of the DS3 frame. When
the Extended-features mode (EMODE), Coding Violation Enable (CVEN) and Excessive Zeros Enable
(EXZEN) control bits in the memory map are set to 1, the Coding Violations Count (CVCNT) function and
Excessive Zeros Count (EXZCNT) functions pin replace the FORCECP and FORCEPP functions, respectively.
The purpose of these pins is to utilize the DS3F's 16-bit counter CVEXZ to count coding violation and/or exces-
sive zeros events. Indications of these events are provided to the DS3F by TranSwitch's ART or ARTE devices
(TXC-02020/02021). The ART's CV output pin indicates both coding violations and excessive zeros. Therefore,
only the CVCNT input pin to the DS3F is required to count both types of event. When the ARTE is used in con-
junction with the DS3F, there are separate CV and EXZ inputs available to the DS3F, which can be or-gated
together in the DS3F's 16-bit counter, if required. The DS3F has an internal 16-bit shadow counter incorpo-
rated into its counter design. This prevents CV or EXZ counts being lost during a read cycle.
The Transmit Frame Reference Generator Block provides reference timing for bit-serial operation. This block
accepts an external 44.736MHz clock signal (TCIN) and derives a clock signal (TCOUT), a framing pulse
(TFOUT), a clock gap signal (TCG) and a data signal (TDOUT). The DS3 data signal consists of framing bits
and zeros elsewhere. An optional input framing pulse (TFIN) is also provided, but is not required for normal
operation.
The DS3F microprocessor bus interface consists of eight bidirectional data and address pins (AD0-AD7),
along with other microprocessor control pins. The microprocessor bus is used to write control information and
to read status information and alarms. When operating in the Extended-features mode the DS3F memory map
contains twenty-one effective addresses (00H-14H), compared with eight (00H-07H) in the Normal mode.
When the DS3F is operating in the Extended-features mode, its many additional features may be activated via
control bits in the memory map. These features include: ability to tri-state all output ports, X-bit inversion,
receive loop timing, receive and transmit Blue Code AIS conditions, FEAC Idle Channel Indication, a receive
FEAC FIFO stack overflow bit, a Severely Errored Frame indication, and double FEAC word handling.
- 5 of 54 -
TXC-03401B-MB
Ed. 6, June 2001
5 Page 
Proprietary TranSwitch Corporation Information for use Solely by its Customers
DATA SHEET
DS3F
TXC-03401B
Symbol
XSC/
XNC
68-Pin
PLCC
Pin No.
66
80-Pin
TQFP
Pin No.
47
I/O/P
O
Type
Name/Function
CMOS
4mA
Transmit Nibble/Serial Clock: Clock signal
derived from the Transmit Reference Generator
Clock (TCIN). For nibble data, this clock (XNC) is
stretched in order to accommodate the 56 over-
head bit positions which are not required by the
external terminal circuitry for the nibble interface
(XNIBn). For serial data, a gapped clock signal
(XSC) is generated and provided on this pin when
control bits SER and TGCEN are both set to 1.
This signal is synchronous with bit 1 in each 85-
bit group (56 overhead bits) in the DS3 frame.
TRANSMIT REFERENCE GENERATOR INTERFACE
Symbol
TDOUT
68-Pin
PLCC
Pin No.
45
80-Pin
TQFP
Pin No.
23
I/O/P
O
Type
TTL
4mA
TCG
46
TFOUT
47
24 O TTL
4mA
25 O TTL
4mA
Name/Function
Transmit Reference Generator Data Output:
DS3 frames are provided on this output that con-
tain either all zeros or all ones. The number of
frames with ones is 7 of every 18 frames. The pat-
tern of the ones is one frame of every three for 15
frames and two of the last 3 of the 18-frame
group; this completes the 7 of 18 pattern.
The purpose of this pattern is to ease the require-
ment to provide an all-ones and all-zeros C-bit
pattern to insure a DS2 frequency that is very
nearly equal to its specified value.
Transmit Reference Generator Clock Gap Sig-
nal: An active low, one clock cycle wide (TCOUT)
signal that is synchronous with bit 1 in each 85-bit
group (56 overhead bits) in the DS3 frame.
Transmit Reference Generator Framing Pulse:
An active low, one clock cycle wide (TCOUT)
pulse that is synchronous with bit 1 in the DS3
frame. May be used as the serial data transmit
framing pulse (XFSI) if properly delayed such that
XFSI is aligned with an overhead-bit clock cycle.
- 11 of 54 -
TXC-03401B-MB
Ed. 6, June 2001
11 Page | ||
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