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GT-6816 Schematic ( PDF Datasheet ) - ETC

Teilenummer GT-6816
Beschreibung SCANNER Chips
Hersteller ETC
Logo ETC Logo 




Gesamt 30 Seiten
GT-6816 Datasheet, Funktion
m GT-6816
.coI. General Descriptions-
t4UThe GT-6816 is an enhanced version of GT-6801, which provides highly integrated System-On-Chip
ee(SOC) solution for high-performance color scanner. The GT-6816 is enhanced not only in the AFE
h(Analog Front End) from 12-bit to 16-bit but also built-in an intelligent power management circuit to
taSmeet both operating and suspend mode for USB bus-powered Scanner. The GT-6816 is also pin to pin
abackward compatible with the GT-6801, providing system designer easy way to upgrade the current
www.Dapplications without changing the hardware design.
II. Features-
² Single-chip integration for high-performance color scanner application
m² On-chip Analog Front End: CDS/AGC and 16-bit ADC Maximum 6MHz
o² On-chip universal TG supports various types of CCD/CIS sensors
² Embedded high-performance RISC controller
.c² On-chip USB transceiver
² Built-in 16KB image line buffers
² PC interface supports : USB/EPP/ECP/BPP
U² No external memory component required for typical application
² Firmware programmable frame size
t4² Intelligent power management meets both operating and suspend mode for USB
bus power
e² On-chip PLL circuits
² Operating clock :48 MHz with external crystal: 6 MHz
e² Operating voltage: Core: 3.3V, I/O: 5V
h² Operating current: Core 80mA, AFE 50mA
² Suspend current: 50 A
S² Package: 128-QFP & 44-QFP
taAFE
.DaCDS
PGA
16-bit ADC
Compression
Engine
www6MHz
PLL
Universal
Timing
Scanner
Image Buffer
Crystal
MOTOR
Generator
Control Logic
eet4U.comI/O RISC
Program
memory
Mask
ROM
Intelligent
Power
Management
PC interface
Parallel port
ECP
EPP
SPP
USB
taShROM
www.Da2KB
1






GT-6816 Datasheet, Funktion
GT-6816
VI.Registers map-
PPCR
PPHAR
PPLAR
PPDR
IVDHPR
IVDLPR
IVIR
HADFR
TGCR
MOD6DR
MOD6PR
MOD16HR
R/W ‘hff
R/W ‘hfe
R/W ‘hfd
R/W ‘hfc
R/W ‘hfb
R/W ‘hfa
R/W ‘hf9
R/W ‘he4
R/W ‘hff00
R/W ‘hff01
R/W ‘hff02
R/W ‘hff03
MOD16LR R/W ‘hff04
ADCLKRR R/W ‘hff05
ADCLKFR R/W ‘hff06
SHR6R
R/W ‘hff07
SHF6R
R/W ‘hff08
SHR8R
R/W ‘hff09
SHF8R
R/W ‘hff0a
SHCR
R/W ‘hff0b
LEDRHR R/W ‘hff0c
LEDRLR R/W ‘hff0d
LEDFHR R/W ‘hff0e
LEDFLR R/W ‘hff0f
LEDCR
R/W ‘hff10
TGMR
R/W ‘hff11
RS1RR
R/W ‘hff12
RS1FR
R/W ‘hff13
RS2RR
R/W ‘hff14
RS2FR
R/W ‘hff15
SHRRR
R/W ‘hff16
SHRFR
R/W ‘hff17
SHSRR
R/W ‘hff18
SHSFR
R/W ‘hff19
H1RR
R/W ‘hff1a
H1FR
R/W ‘hff1b
H2RR
R/W ‘hff1c
H2FR
R/W ‘hff1d
CLAMP0RR R/W ‘hff1e
CLAMP0FR R/W ‘hff1f
Parallel port control register
Parallel port high address register
Parallel port low address register
Parallel port data register
Image valid data high pointer register
Image valid data low pointer register
Image valid indication register
Host access device flag register
TG Control Register
Modulo 6 bit for dot clock
Modulo 6 bit for pixel clock
Modulo 16 bit high byte
Modulo 16 bit low byte
ADCLK rise register
ADCLK fall register
SH(TG) setup register(reference to 6bit counter)
SH(TG) setup register(reference to 6bit counter)
SH(TG) setup register(reference to 16bit counter)
SH(TG) setup register(reference to 16bit counter)
SH(TG) configuration register
LED rise high register(reference to 16bit counter)
LED rise low register(reference to 16bit counter)
LED fall high register(reference to 16bit counter)
LED fall low register(reference to 16bit counter)
LED configuration register
TG Mask register
RS1 rise register
RS1 fall register
RS2 rise register
RS2 fall register
SHR rise register
SHR fall register
SHS rise register
SHS fall register
H1 rise register
H1 fall register
H2 rise register
H2 fall register
CLAMP 0 rise register
CLAMP 0 fall register
6

6 Page









GT-6816 pdf, datenblatt
GT-6816
Referenced period for 6-bits dot clock counter:
CPU Read/Write
Address: FF01H
Bit Reset Description
7:6 2’b0 Reserved
Defines the referenced period (N+1) cycles of the 6 bits dot clock counter.
5:0 6’b0 The 6-bits dot clock counter is referenced by master clock (48MHz). Dot
clock is defined by this N+1 cycles referenced to 6-bits dot clock counter.
Referenced period for 6-bits pixel clock counter:
CPU Read/Write
Address: FF02H
Bit Reset Description
7:6 2’b0 Reserved
Defines the referenced period (N+1) cycles of the 6 bits pixel clock
counter. The 6-bits pixel clock counter is referenced by master clock
(48MHz). Pixel clock is defined by this N+1 cycles referenced to 6-bits
5:0 6’b0
pixel clock counter.
The programmable timing control signal for sensor and AFE are
referenced to pixel clock.
Referenced period high byte for 16-bits counter of timing generator:
CPU Read/Write
Address: FF03H
Bit Reset Description
7:0 8’b0 Period for 16-bits counter high byte
Referenced period low byte for 16-bits counter of timing generator:
Address: FF04H
Bit Reset Description
Period for 16-bits counter low byte.
These two registers define the period (N+1) cycles of 16-bits counter
7:0 8’b0
referenced to pixel clock. All programmable timing control signals are
referenced to this 16-bits counter.
AFE ADCLK rising phase control
CPU Read/Write
Address: FF05H
Bit Reset Description
7:6 2’b0 Reserved
5:0 6’b0 Define ADCLK rising phase referenced to 6-bits dot clock counter
AFE ADCLK falling phase control
12

12 Page





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