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MX10E8050IA Schematic ( PDF Datasheet ) - Macronix

Teilenummer MX10E8050IA
Beschreibung Microcontroller
Hersteller Macronix
Logo Macronix Logo 




Gesamt 30 Seiten
MX10E8050IA Datasheet, Funktion
.com PRELIMINARY
ataSheet4UMX10E8050I
w.D MX10E8050IA
ww .comMajor Difference
Feature
t4UProduct
eeMX10E8050IPC
hMX10E8050IQC
SMX10E8050IUC
Default
Clock mode
x6
x 12
ataMX10E8050IAQC
x 12
ISP
UART
I2C
IAP
YES
YES
Package
44 Pin PDIP
44 Pin PLCC
44 Pin LQFP
44 Pin PLCC
www.D www.DataSheet4U.comP/N:PM0887 Specifications subject to change without notice, contact your sales representatives for the most update information.REV. 1.6, DEC. 21, 2004
1






MX10E8050IA Datasheet, Funktion
PRELIMINARY
MX10E8050I /
MX10E8050IA
BLOCK DIAGRAM
P4.0-P4.3
P0.0-P0.7
P2.0-P2.7
Vcc
Vss
PORT 4
PORT 4
PORT 0
PORT 2
DRIVERS
LATCH
DRIVERS
DRIVERS
RAM
PWM
PORT 0
LATCH
PORT 2
LATCH
ROM
PSEN
ALE
EA
RST
ACC
B
REGISTER
TMP2
ALU
PSW
STACK
POINTER
T3
WATCHDOG
TIMER
TMP1
T0/T1/T2
SFRs
TIMERS
PROGRAM
ADDR.
REGISTER
BUFFER
PC
INCREMENTER
PROGRAM
COUNTER
TIMING
AND
CONTROL
PORT 1
LATCH
DPTR
PORT 3
I2C
LATCH
OSC.
PORT 1
DRIVERS
Input Filter
Output Stage
PORT 3
DRIVERS
XTAL1
XTAL2
P1.0-P1.7
P3.0-P3.7
P/N:PM0887 Specifications subject to change without notice, contact your sales representatives for the most update information. REV. 1.6, DEC. 21, 2004
6

6 Page









MX10E8050IA pdf, datenblatt
PRELIMINARY
MX10E8050I /
MX10E8050IA
AUXR (8EH)
EXTRAM
A0
- EXTRAM : External RAM Select Switch. Set 1 to select (MOVX) the external RAM directly.
Default is 0 to switch (MOVX) to external RAM only when the address is larger than 1k.
- AO : Turn off ALE output in internal execution mode.
( 1 : Turn off )
( 0 : Turn on )
Watchdog Timer/WDT/T3 (FFH)
- WDT consists of an 11-bit prescaler and an 8-bit timer formed by SFR T3.
EBTCON (EBH)
/EW
- /EW: After reset, /EW bit is set, and WDT is disable.
POWER CONTROL Register/PCON (87H)
SMOD1 SMOD0
X
WLE
GF1
GF0 PD
IDL
- SMOD1: Double baud rate bit for UART.
- SMOD0: Frame error detection bit.
- WLE: Watchdog load enable. This flag must be set prior to loading WDT and is cleared when WDT is loaded.
- GF1/GF0: general-purpose flag bit.
- PD: Power-down bit. Setting it activates power-down mode.
- IDL: Idle mode bit. Setting it activates idle mode.
- The CPU & Peripheral status during 2 power saving mode:
CPU
Int,Timer.
Oscillator ckt
Idle mode
OFF
ON
ON
Power-down mode
OFF
OFF
OFF
P/N:PM0887 Specifications subject to change without notice, contact your sales representatives for the most update information. REV. 1.6, DEC. 21, 2004
12

12 Page





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