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MX10EXA Schematic ( PDF Datasheet ) - Macronix International

Teilenummer MX10EXA
Beschreibung XA 16-bit Microcontroller Family 64K Flash/2K RAM
Hersteller Macronix International
Logo Macronix International Logo 




Gesamt 30 Seiten
MX10EXA Datasheet, Funktion
FEATURE
PRELIMINARY
MX10EXA
XA 16-bit Microcontroller Family
64K Flash/2K RAM, Watchdog, 2UARTs
• 4.5V to 5.5V
• 64K bytes of on-chip Flash program memory with In-
System Programming capability
• Five Flash blocks = two 8k byte blocks and three 16k
byte blocks
• Single supply voltage In-System Programming of the
Flash memory, (VPP=VDD or VPP=12V ifdesired)
• Boot ROM contains low level Flash programming
routines for In-Application Programming and a default
serial loader using the UART
• 2048 bytes of on-chip data RAM
• Supports off-chip program and data addressing up to 1
megabyte (20 address lines)
• Three standard counter/timers with enhanced features
All timers have a toggle output capability
• Watchdog timer
• Two enhanced UARTs with independent baud rates
• Seven software interrupts
• Four 8-bit I/O ports, with 4 programmable output
configurations for each pin
• 30 MHz operating frequency at 5V
• Power saving operating modes: Idle and Power-
Down.Wake-Up from power-down via an external inter-
rupt is supported.
• 44-pin PLCC (MX10EXAQC) and 44-pin LQFP
(MX10EXAUC) packages
GENERAL DESCRIPTION
The MX10EXA is a member of Philips’ 80C51 XA
(eXtended Architecture) family of high performance 16-
bit single-chip microcontrollers.
The MX10EXA contains 64k bytes of Flash program
memory, and provides three general purpose timers/
counters, a watchdog timer, dual UARTs, and four gen-
eral purpose I/O ports with programmable output con-
figurations.
A default serial loader program in the Boot ROM allows
In-System Programming (ISP) of the Flash memory with-
out the need for a loader in the Flash code. User pro-
grams may erase and reprogram the Flash memory at
will through the use of standard routines contained in
the Boot ROM (In-Application Programming).
PIN CONFIGURATIONS
44 PLCC
P1.5/TxD1
P1.6/T2
P1.7/T2EX
RST
P3.0/RxD0
NC
P3.1/TxD0
P3.2/INT0
P3.3/INT1
P3.4/T0
P3.5/T1/BUSW
6
7
12
17
18
1 44
MX10EXAQC
23
40
39 P0.4/A8D4
P0.5/A9D5
P0.6/A10D6
P0.7/A11D7
EA/VPP/WAIT
34 NC
ALE
PSEN
P2.7/A19D15
P2.6/A18D14
29 P2.5/A17D13
28
44 LQFP
P1.5/TxD1
P1.6/T2
P1.7/T2EX
RST
P3.0/RxD0
NC
P3.1/TxD0
P3.2/INT0
P3.3/INT1
P3.4/T0
P3.5/T1/BUSW
44
1
11
12
MX10EXAUC
34
33 P0.4/A8D4
P0.5/A9D5
P0.6/A10D6
P0.7/A11D7
EA/VPP/WAIT
NC
ALE
PSEN
P2.7/A19D15
P2.6/A18D14
23 P2.5/A17D13
22
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MX10EXA Datasheet, Funktion
MX10EXA
NAME DESCRIPTION
SFR BIT FUNCTIONS AND ADDRESSES
Reset
address MSB
LSB VALUE
227 226 225 224 223 222 221 220
PCON* Power control register
404 ---
--- ---
---
--- --- PD IDL 00
PSWH* Program status word
20F 20E 20D 20C 20B 20A 209 208
401 SM TM RS1 RS0 IM3 IM2 IM1 I M0 Note 2
(high byte)
PSWL* Program status word
207 206 205 204 203 202 201 200
400 C
AC --- --- --- V N Z Note 2
(low byte)
217 216 215 214 213 212 211 210
PSW51* 80C51 compatible PSW
402 C
RTH0 Timer 0 extended reload, 455
high byte
RTH1 Timer 1 extended reload, 457
high byte
RTL0 Timer 0 extended reload, 454
low byte
RTL1 Timer 1 extended reload, 456
AC F0
RS1 RS0 V
F1 P
Note 3
00
00
00
00
low byte
307 306 305 304 303 302 301 300
S0CON* Serial port 0 control register 420 SM0_0 SM1_0 SM2_0 REN_0 TB8_0 RB8_0 TI_0 RI_0 00
30F 30E 30D 30C 30B 30A 309 308
S0STAT* Serial port 0 extended status 421 --- --- --- --- FE0 BR0 OE0 STINT0 00
S0BUF Serial port 0 buffer register 460
x
S0ADDR Serial port 0 address register 461
S0ADEN Serial port 0 address enable 462
0
00
register
327 326 325 324 323 322 321 320
S1CON* Serial port 1 control register 424 SM0_1 SM1_1 SM2_1 REN_1 TB8_1 RB8_1 TI_1 RI_1 00
32F 32E 32D 32C 32B 32A 329 328
S1STAT* Serial port 1 extended status 425 --- --- --- --- FE1 BR1 OE1 STINT1 00
S1BUF Serial port 1 buffer register 464
x
S1ADDR Serial port 1 address register 465
S1ADEN Serial port 1 address enabler 466
00
00
register
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MX10EXA pdf, datenblatt
MX10EXA
FMIDLE
The FMIDLE bit in the AUXR register allows saving addi-
tional power by turning off the Flash memory when the
CPU is in the Idle mode. This must be done just prior to
initiating the Idle mode, as shown below.
OR AUXR, #$40 ;Set Flash memory to idle
mode.
OR PCON, #$0l ;Turn on Idle mode.
. . ;Execution resumes here when
Idle mode terminates.
When the Flash memory is put into the Idle mode by
setting FMIDLE, restarting the CPU upon exiting Idle
mode takes slightly longer, about 3 microseconds. How-
ever, the standby current consumed by the Flash memory
is reduced from about 8mA to about 1mA.
Default Loader
A default loader that accepts programming commands
in a predetermined format is contained permanently in
the Boot ROM. A factory fresh device will enter this loader
automatically if it is powered up without first being pro-
grammed by the user. Loader commands include func-
tions such as erase block; program Flash memory; read
Flash memory; and blank check.
Boot Vector
The XA contains two special FLASH registers: the BOOT
VECTOR and the STATUS BYTE.
The "Boot Vector" allows forcing the execution of a user
supplied Flash loader upon reset, under two specific sets
of conditions. At the falling edge of reset, the XA exam-
ines the contents of the Status Byte. If the Status Byte
is set to zero, power-up execution starts at location
0000H, which is the normal start address of the user’s
application code.
When the Status Byte is set to a value other than zero,
the Boot Vector is used as the reset vector (4 bytes),
including the Boot Program Counter (BPC) and the Boot
PSW (BPSW).The factory default settings are 8000h for
the BPSW and F800h for the BPC, which corresponds
to the address F900h for the factory masked-ROM ISP
boot loader. The Status Byte is automatically set to a
non-zero value when a programming error occurs. A cus-
tom boot loader can be written with the Boot Vector set
to the custom boot loader.
NOTE: When erasing the Status Byte or Boot Vector,
these bytes are erased at the same time. It is necessary
to reprogram the Boot Vector after erasing and updating
the Status Byte.
Hardware Activation of the Boot Vector
Program execution at the Boot Vector may also be forced
from outside of the microcontroller by setting the correct
state on a few pins. While Reset is asserted, the PSEN
pin must be pulled low, the ALE pin allowed to float high
(need not be pulled up externally), and the EA pin driven
to a logic high (or up to VPP).Then reset may be released.
This is the same effect as having a non-zero status byte.
This allows building an application that will normally ex-
ecute the end user’s code but can be manually forced
into ISP operation. The Boot ROM is enabled when use
of the Boot Vector is forced as described above, so the
branch may go to the default loader. Conversely, user
code in the top 2k bytes of the Flash memory may not
be executed when the Boot Vector is used.
If the factory defauolt setting for the BPC (F800h) is
changed, it will no longer point to the ISP masked-ROM
boot loader code. If this happens, the only possible way
to change the contents of the Boot Vector is through the
parallel programming method, provided that the end user
application does not contain a customized loader that
provides for erasing and reprogramming of the Boot Vec-
tor and Status Byte.
After programming the FLASH, the status byte should
be erased to zero in order to allow execution of the user’s
application code beginning at address 0000H.
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REV. 1.1, MAY 05, 1999
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12 Page





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