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PDF CY7C1231F Data sheet ( Hoja de datos )
| Número de pieza | CY7C1231F | |
| Descripción | 2Mbit Flow-Through SRAM | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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.com CY7C1231F
Sheet4U 2-Mbit (128K x 18) FlowN-tohBroLu™ghASrcRhAitMecwtuirtehFeatures
ta• Can support up to 117-MHz bus operations with zero
await states
.D— Data is transferred on every clock
w• Pin compatible and functionally equivalent to ZBT™
wdevices
w • Internally self-timed output buffer control to eliminate
the need to use OE
m• Registered inputs for flow-through operation
o• Byte Write capability
.c• 128K x 18 common I/O architecture
• Single 3.3V power supply
• Fast clock-to-output times
U— 7.5 ns (for 117-MHz device)
t4— 8.5 ns (for 100-MHz device)
• Clock Enable (CEN) pin to suspend operation
e• Synchronous self-timed writes
• Asynchronous Output Enable
e• JEDEC-standard 100 TQFP package
h• Burst Capability—linear or interleaved burst order
• Low standby power
Functional Description[1]
The CY7C1231F is a 3.3V, 128K x 18 Synchronous
Flow-through Burst SRAM designed specifically to support
unlimited true back-to-back Read/Write operations without the
insertion of wait states. The CY7C1231F is equipped with the
advanced No Bus Latency™ (NoBL™) logic required to
enable consecutive Read/Write operations with data being
transferred on every clock cycle. This feature dramatically
improves the throughput of data through the SRAM, especially
in systems that require frequent Write-Read transitions.
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. The clock input is qualified by
the Clock Enable (CEN) signal, which when deasserted
suspends operation and extends the previous clock cycle.
Maximum access delay from the clock rise is 7.5 ns (117-MHz
device).
Write operations are controlled by the two Byte Write Select
(BW[A:B]) and a Write Enable (WE) input. All writes are
conducted with on-chip synchronous self-timed write circuitry.
Three synchronous Chip Enables (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) provide for easy bank
selection and output three-state control. In order to avoid bus
contention, the output drivers are synchronously three-stated
during the data portion of a write sequence.
taSLogic Block Diagram
aCLK
.DCEN
A0, A1, A
MODE
C
CE
ADDRESS
REGISTER
A1
A0
D1
D0
ADV/LD
C
WRITE ADDRESS
REGISTER
Q1
Q0
A1'
A0'
BURST
LOGIC
wADV/LD
wBWA
BWB
w .comWE
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
WRITE
DRIVERS
MEMORY
ARRAY
S
E
N
S
E
A
M
P
S
O
U
T
DP
AU
TT
A
B
SU
TF
EF
EE
RR
IS
NE
G
DQs
DQPA
DQPB
et4UOE
eCE1
hCE2
CE3
SZZ
READ LOGIC
SLEEP
CONTROL
INPUT E
REGISTER
taNote:
a1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.
ww.DCypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
wDocument #: 38-05437 Rev. *A
Revised April 5, 2004
1 page  
CY7C1231F
Sleep Mode
Interleaved Burst Sequence
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CE1, CE2, and CE3, must remain inactive for
the duration of tZZREC after the ZZ input returns LOW.
Linear Burst Address Table (MODE = GND)
First
Address
A1, A0
00
01
10
11
Second
Address
A1, A0
01
10
11
00
Third
Address
A1, A0
10
11
00
01
Fourth
Address
A1, A0
11
00
01
10
First
Address
A1, A0
00
01
10
11
Second
Address
A1, A0
01
00
11
10
Third
Address
A1, A0
10
11
00
01
Fourth
Address
A1, A0
11
10
01
00
ZZ Mode Electrical Characteristics
Parameter
IDDZZ
tZZS
tZZREC
tZZI
tRZZI
Description
Snooze mode standby current
Device operation to ZZ
ZZ recovery time
ZZ Active to snooze current
ZZ inactive to exit snooze current
Truth Table[2, 3, 4, 5, 6, 7, 8]
Test Conditions
ZZ > VDD − 0.2V
ZZ > VDD − 0.2V
ZZ < 0.2V
This parameter is sampled
This parameter is sampled
Min.
2tCYC
0
Max.
40
2tCYC
2tCYC
Unit
mA
ns
ns
ns
ns
Operation
Deselect Cycle
Address
Used CE1 CE2 CE3 ZZ ADV/LD WE BWX OE CEN CLK
DQ
None H X X L L X X X L L->H Three-State
Deselect Cycle
None X X H L L X X X L L->H Three-State
Deselect Cycle
None X L X L L X X X L L->H Three-State
Continue Deselect Cycle
None X X X L H X X X L L->H Three-State
READ Cycle (Begin Burst)
External L H L L L H X L L L->H Data Out (Q)
READ Cycle (Continue Burst)
Next X X X L H X X L L L->H Data Out (Q)
NOP/DUMMY READ (Begin Burst) External L H L L L H X H L L->H Three-State
DUMMY READ (Continue Burst)
Next X X X L H X X H L L->H Three-State
WRITE Cycle (Begin Burst)
External L H L L L L L X L L->H Data In (D)
WRITE Cycle (Continue Burst)
Next X X X L H X L X L L->H Data In (D)
NOP/WRITE ABORT (Begin Burst)
None L H L L L L H X L L->H Three-State
WRITE ABORT (Continue Burst)
Next X X X L H X H X L L->H Three-State
IGNORE CLOCK EDGE (Stall)
Current X X X L X X X X H L->H
–
SNOOZE MODE
None X X X H
X
X X X X X Three-State
Notes:
2. X = “Don't Care.” H = Logic HIGH, L = Logic LOW. BWx = 0 signifies at least one Byte Write Select is active, BWx = Valid signifies that the desired byte write
selects are asserted, see Truth Table for details.
3. Write is defined by BW[A:B], and WE. See Truth Table for Read/Write.
4. When a write cycle is detected, all I/Os are three-stated, even during byte writes.
5. The DQs and DQP[A:B] pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
6. CEN = H, inserts wait states.
7. Device will power-up deselected and the I/Os in a three-state condition, regardless of OE.
8.
OE
OE
is
is
asynchronous and is
inactive or when the
not sampled with the clock rise.
device is deselected, and DQs
It is
and
masked internally during write cycles.
DQP[A:B] = data when OE is active.
During
a
read
cycle
DQs
and
DQP[A:B]
=
Three-state
when
Document #: 38-05437 Rev. *A
Page 5 of 12
5 Page 
Package Diagram
100-lead Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101
CY7C1231F
51-85050-*A
NoBL and No Bus Latency are trademarks of Cypress Semiconductor Corporation. ZBT is a trademark of Integrated Device
Technology. All product and company names mentioned in this document are the trademarks of their respective holders.
Document #: 38-05437 Rev. *A
Page 11 of 12
© Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet CY7C1231F.PDF ] | |
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