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XQ4005E Schematic ( PDF Datasheet ) - Xilinx

Teilenummer XQ4005E
Beschreibung QPRO XQ4000E/EX QML High-Reliability FPGAs
Hersteller Xilinx
Logo Xilinx Logo 




Gesamt 30 Seiten
XQ4005E Datasheet, Funktion
0
R QPRO XQ4000E/EX
QML High-Reliability FPGAs
DS021 (v2.2) June 25, 2000
02
Product Features
• Certified to MIL-PRF-38535, appendix A QML
(Qualified Manufacturers Listing)
• Also available under the following Standard Microcircuit
Drawings (SMD)
- XC4005E 5962-97522
- XC4010E 5962-97523
- XC4013E 5962-97524
- XC4025E 5962-97525
- XC4028EX 5962-98509
• For more information contact the Defense Supply
Center Columbus (DSCC)
http://www.dscc.dla.mis/v/va/smd/smdsrch.html
• System featured Field-Programmable Gate Arrays
- Select-RAMTM memory: on-chip ultra-fast RAM with
· Synchronous write option
· Dual-port RAM option
- Abundant flip-flops
- Flexible function generators
- Dedicated high-speed carry logic
- Wide edge decoders on each edge
- Hierarchy of interconnect lines
- Internal 3-state bus capability
- Eight global low-skew clock or signal distribution
networks
System Performance beyond 60 MHz
Flexible Array Architecture
Low Power Segmented Routing Architecture
Systems-Oriented Features
- IEEE 1149.1-compatible boundary scan logic
support
- Individually programmable output slew rate
- Programmable input pull-up or pull-down resistors
- 12 mA sink current per XQ4000E/EX output
Product Specification
Configured by Loading Binary File
- Unlimited reprogrammability
Readback Capability
- Program verification
- Internal node observability
Backward Compatible with XC4000 Devices
Development System runs on most common computer
platforms
- Interfaces to popular design environments
- Fully automatic mapping, placement and routing
- Interactive design editor for design optimization
Available Speed Grades:
- XQ4000E -3 for plastic packages only
- -4 for ceramic packages only
- XQ4028EX -4 for all packages
More Information
For more information refer to Xilinx XC4000E and XC4000X
series Field Programmable Gate Arrays product specifica-
tion. This data sheet contains pinout tables for XQ4010E
only. Refer to Xilinx web site for pinout tables for other
devices. (Pinouts for XQ4000E/EX are identical to
XC4000E/EX.)
(http://www.xilinx.com/partinfo/databook.htm)
© 2000 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS021 (v2.2) June 25, 2000
Product Specification
www.xilinx.com
1-800-255-7778
1






XQ4005E Datasheet, Funktion
QPRO XQ4000E/EX QML High-Reliability FPGAs
R
XQ4000E Wide Decoder Switching Characteristic Guidelines
Testing of switching parameters is modeled after testing
methods specified by MIL-M-38510/605. All devices are
100% functionally tested. Internal timing parameters are
derived from measuring internal test patterns. Listed below
are representative values. For more specific, more precise,
and worst-case guaranteed data, use the values reported
by the static timing analyzer (TRCE in the Xilinx Develop-
ment System) and back-annotated to the simulation netlist.
These path delays, provided as a guideline, have been
extracted from the static timing analyzer report. All timing
parameters assume worst-case operating conditions (sup-
ply voltage and junction temperature). Values apply to all
XQ4000E devices unless otherwise noted.
The following guidelines reflect worst-case values over the
recommended operating conditions.
Symbol
Description(1,2)
Device
-3 -4
Max Max Units
TWAF Full length, both pull-ups, inputs from IOB I-pins
XQ4005E
XQ4010E
- 9.5
9.0 15.0
ns
ns
XQ4013E 11.0 16.0 ns
XQ4025E
- 18.0 ns
TWAFL Full length, both pull-ups, inputs from internal logic
XQ4005E
XQ4010E
- 12.5
11.0 18.0
ns
ns
XQ4013E 13.0 19.0 ns
XQ4025E
- 21.0 ns
TWAO Half length, one pull-up, inputs from IOB I-pins
XQ4005E
XQ4010E
- 10.5
10.0 16.0
ns
ns
XQ4013E 12.0 17.0 ns
XQ4025E
- 19.0 ns
TWAOL Half length, one pull-up, inputs from internal logic
XQ4005E
XQ4010E
- 12.5
12.0 18.0
ns
ns
XQ4013E 14.0 19.0 ns
XQ4025E
- 21.0 ns
Notes:
1. These delays are specified from the decoder input to the decoder output.
2. Fewer than the specified number of pull-up resistors can be used, if desired. Using fewer pull-ups reduces power consumption but
increases delays. Use the static timing analyzer to determine delays if fewer pull-ups are used.
6
www.xilinx.com
DS021 (v2.2) June 25, 2000
1-800-255-7778
Product Specification

6 Page









XQ4005E pdf, datenblatt
QPRO XQ4000E/EX QML High-Reliability FPGAs
XQ4000E CLB Level-Sensitive RAM Timing Characteristics
WRITE
ADDRESS
WE
TAS
DATA IN
READ WITHOUT WRITE
X,Y OUTPUTS VALID
TILO
TWC
TWP
TAH
TDS
REQUIRED
TDH
VALID
READ, CLOCKING DATA INTO FLIP-FLOP
CLOCK
TICK
XQ,YQ OUTPUTS
READ DURING WRITE
WRITE ENABLE
DATA IN
(stable during WE)
X,Y OUTPUTS
VALID (OLD)
VALID
TWO
TCH
TCKO
TWP
VALID (NEW)
TDH
VALID
DATA IN
(changing during WE)
X,Y OUTPUTS
OLD
VALID
(PREVIOUS)
TWO
VALID
(OLD)
TDO
READ DURING WRITE, CLOCKING DATA INTO FLIP-FLOP
WRITE ENABLE
DATA IN
TWCK
TDCK
TWP
NEW
VALID
(NEW)
CLOCK
XQ,YQ OUTPUTS
TCKO
DS021_03_060100
R
12
www.xilinx.com
DS021 (v2.2) June 25, 2000
1-800-255-7778
Product Specification

12 Page





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