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PDF PIC16F872 Data sheet ( Hoja de datos )
| Número de pieza | PIC16F872 | |
| Descripción | 28-Pin / 8-Bit CMOS FLASH Microcontroller | |
| Fabricantes | Microchip Technology | |
| Logotipo |  |
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PIC16F872
28-Pin, 8-Bit CMOS FLASH Microcontroller
Devices Included in this Data Sheet:
• PIC16F872
Microcontroller Core Features:
• High-performance RISC CPU
• Only 35 single word instructions to learn
• All single cycle instructions except for program
branches which are two cycle
• Operating speed: DC - 20 MHz clock input
DC - 200 ns instruction cycle
• 2K x 14 words of FLASH Program Memory
128 x 8 bytes of Data Memory (RAM)
64 x 8 bytes of EEPROM Data Memory
• Pinout compatible to the PIC16C72A
• Interrupt capability (up to 10 sources)
• Eight level deep hardware stack
• Direct, indirect and relative addressing modes
• Power-on Reset (POR)
• Power-up Timer (PWRT) and Oscillator Start-up
Timer (OST)
• Watchdog Timer (WDT) with its own on-chip RC
oscillator for reliable operation
• Programmable code-protection
• Power saving SLEEP mode
• Selectable oscillator options
• Low-power, high-speed CMOS FLASH/EEPROM
technology
• Fully static design
• In-Circuit Serial Programming™ (ICSP) via two
pins
• Single 5V In-Circuit Serial Programming capability
• In-Circuit Debugging via two pins
• Processor read/write access to program memory
• Wide operating voltage range: 2.0V to 5.5V
• High Sink/Source Current: 25 mA
• Commercial and Industrial temperature ranges
• Low-power consumption:
- < 2 mA typical @ 5V, 4 MHz
- 20 µA typical @ 3V, 32 kHz
- < 1 µA typical standby current
Pin Diagram
DIP, SOIC, SSOP
MCLR/VPP/THV
RA0/AN0
RA1/AN1
RA2/AN2/VREF-
RA3/AN3/VREF+
RA4/T0CKI
RA5/AN4/SS
VSS
OSC1/CLKIN
OSC2/CLKOUT
RC0/T1OSO/T1CKI
RC1/T1OSI
RC2/CCP1
RC3/SCK/SCL
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28 RB7/PGD
27 RB6/PGC
26 RB5
25 RB4
24 RB3/PGM
23 RB2
22 RB1
21 RB0/INT
20 VDD
19 VSS
18 RC7
17 RC6
16 RC5/SDO
15 RC4/SDI/SDA
Peripheral Features:
• Timer0: 8-bit timer/counter with 8-bit prescaler
• Timer1: 16-bit timer/counter with prescaler,
can be incremented during sleep via external
crystal/clock
• Timer2: 8-bit timer/counter with 8-bit period
register, prescaler and postscaler
• One Capture, Compare, PWM module
- Capture is 16-bit, max. resolution is 12.5 ns
- Compare is 16-bit, max. resolution is 200 ns
- PWM max. resolution is 10-bit
• 10-bit multi-channel Analog-to-Digital converter
• Synchronous Serial Port (SSP) with SPI™ (Master
Mode) and I2C™ (Master/Slave)
• Brown-out detection circuitry for Brown-out Reset
(BOR)
© 1999 Microchip Technology Inc.
Preliminary
DS30221A-page 1
1 page  
PIC16F872
1.0 DEVICE OVERVIEW
This document contains device-specific information.
Additional information may be found in the PICmicro™
Mid-Range Reference Manual, (DS33023), which may
be obtained from your local Microchip Sales Represen-
tative or downloaded from the Microchip website. The
Reference Manual should be considered a comple-
FIGURE 1-1:
Device
PIC16F872
PIC16F872 BLOCK DIAGRAM
Program
FLASH
2K
Data Memory
128 Bytes
Data
EEPROM
64 Bytes
mentary document to this data sheet, and is highly rec-
ommended reading for a better understanding of the
device architecture and operation of the peripheral
modules.
This data sheet covers the PIC16F872 device. The
PIC16F872 is a 28-pin device and its block diagram is
shown in Figure 1-1.
FLASH
Program
Memory
13
Program Counter
8 Level Stack
(13-bit)
Data Bus
8
RAM
File
Registers
Program
Bus
14
Instruction reg
RAM Addr (1) 9
Addr MUX
Direct Addr 7
Indirect
8 Addr
FSR reg
STATUS reg
8
Instruction
Decode &
Control
OSC1/CLKIN
OSC2/CLKOUT
Timing
Generation
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
Brown-out
Reset
In-Circuit
Debugger
Low-Voltage
Programming
3 MUX
ALU
8
W reg
PORTA
PORTB
PORTC
RA0/AN0
RA1/AN1
RA2/AN2/VREF-
RA3/AN3/VREF+
RA4/T0CKI
RA5/AN4/SS
RB0/INT
RB1
RB2
RB3/PGM
RB4
RB5
RB6/PGC
RB7/PGD
RC0/T1OSO/T1CKI
RC1/T1OSI
RC2/CCP1
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
RC6
RC7
Timer0
Timer1
MCLR VDD, VSS
Timer2
10-bit A/D
Data EEPROM
CCP1
Synchronous
Serial Port
Note 1: Higher order bits are from the STATUS register.
© 1999 Microchip Technology Inc.
Preliminary
DS30221A-page 5
5 Page 
PIC16F872
TABLE 2-1: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR,
BOR
Value on
all other
resets
(2)
Bank 2
100h(3)
101h
102h(3)
103h(3)
104h(3)
105h
106h
107h
108h
109h
10Ah(1,3)
10Bh(3)
10Ch
10Dh
10Eh
10Fh
INDF
TMR0
PCL
STATUS
FSR
—
PORTB
—
—
—
PCLATH
INTCON
EEDATA
EEADR
EEDATH
EEADRH
Addressing this location uses contents of FSR to address data memory (not a physical register)
Timer0 module’s register
Program Counter's (PC) Least Significant Byte
IRP RP1 RP0
TO
PD
Z DC
C
Indirect data memory address pointer
Unimplemented
PORTB Data Latch when written: PORTB pins when read
Unimplemented
Unimplemented
Unimplemented
— — — Write Buffer for the upper 5 bits of the Program Counter
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
EEPROM data register
EEPROM address register
— — EEPROM data register high byte
— — — EEPROM address register high byte
0000 0000 0000 0000
xxxx xxxx uuuu uuuu
0000 0000 0000 0000
0001 1xxx 000q quuu
xxxx xxxx uuuu uuuu
——
xxxx xxxx uuuu uuuu
——
——
——
---0 0000 ---0 0000
0000 000x 0000 000u
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
Bank 3
180h(3)
INDF
Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000
181h
OPTION_REG RBPU INTEDG T0CS
T0SE
PSA
PS2 PS1
PS0 1111 1111 1111 1111
182h(3)
PCL
Program Counter's (PC) Least Significant Byte
0000 0000 0000 0000
183h(3)
STATUS
IRP RP1 RP0
TO
PD
Z DC
C 0001 1xxx 000q quuu
184h(3)
FSR
Indirect data memory address pointer
xxxx xxxx uuuu uuuu
185h
—
Unimplemented
——
186h
TRISB
PORTB Data Direction Register
1111 1111 1111 1111
187h
—
Unimplemented
——
188h
—
Unimplemented
——
189h
—
Unimplemented
——
18Ah(1,3) PCLATH
—
—
— Write Buffer for the upper 5 bits of the Program Counter
---0 0000 ---0 0000
18Bh(3) INTCON
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF 0000 000x 0000 000u
18Ch
EECON1
EEPGD
—
—
—
WRERR WREN
WR
RD x--- x000 x--- u000
18Dh
EECON2
EEPROM control register2 (not a physical register)
---- ---- ---- ----
18Eh
—
Reserved maintain clear
0000 0000 0000 0000
18Fh
—
Reserved maintain clear
0000 0000 0000 0000
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as ’0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose
contents are transferred to the upper byte of the program counter.
2: Other (non power-up) resets include external reset through MCLR and Watchdog Timer Reset.
3: These registers can be addressed from any bank.
4: These bits are reserved; always maintain these bits clear.
© 1999 Microchip Technology Inc.
Preliminary
DS30221A-page 11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet PIC16F872.PDF ] | |
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