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AD6650 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD6650
Beschreibung Diversity IF to Baseband GSM/EDGE Narrowband Receiver
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 30 Seiten
AD6650 Datasheet, Funktion
AD6650 Diversity IF-to-Baseband
GSM/EDGE Narrow-Band Receiver
AD6650
FEATURES
116 dB dynamic range
Digital VGA
I/Q demodulators
Active low-pass filters
Dual wideband ADC
Programmable decimation and channel filters
VCO and phase-locked loop circuitry
Serial data output ports
Intermediate frequencies of 70 MHz to 260 MHz
10 dB noise figure
+43 dBm input IP2 at 70 MHz IF
−9.5 dBm input IP3 at 70 MHz IF
3.3 V I/O and CMOS core
Microprocessor interface
JTAG boundary scan
APPLICATIONS
PHS or GSM/EDGE single carrier, diversity receivers
Microcell and picocell systems
Wireless local loop
Smart antenna systems
Software radios
In-building wireless telephony
PRODUCT DESCRIPTION
The AD6650 is a diversity intermediate frequency-to-baseband
(IF-to-baseband) receiver for GSM/EDGE. This narrow-band
receiver consists of an integrated DVGA, IF-to-baseband I/Q
demodulators, low-pass filtering, and a dual wideband ADC.
The chip can accommodate IF input from 70 MHz to 260 MHz.
The receiver architecture is designed such that only one external
surface acoustic wave (SAW) filter for main and one for diversity
are required in the entire receive signal path to meet GSM/EDGE
blocking requirements.
Digital decimation and filtering circuitry provided on-chip
remove unwanted signals and noise outside the channel of
interest. Programmable RAM coefficient filters allow antialiasing,
matched filtering, and static equalization functions to be combined
in a single cost-effective filter. The output of the channel filters
is provided to the user via serial output I/Q data streams.
AIN
VGA
AIN
CPOUT
LF
VLDO
PLL/
VCO
BIN
VGA
BIN
0
/4 90
FUNCTIONAL BLOCK DIAGRAM
TWEAK GAIN
DAC
I
LPF
MUX
LPF
Q
AGC
RELIN
CTRL
12-BIT
ADC
COARSE
DCC
LP
FILTER
4TH
ORDER
CIC
7TH
ORDER
IIR
REF
LPF
LPF
JTAG
Q
MUX
12-BIT
ADC
COARSE
DCC
I
DAC
TWEAK GAIN
CLK
DIVIDER
AGC
RELIN
CTRL
4TH
ORDER
CIC
7TH
ORDER
IIR
LP
FILTER
AD6650 GSM/
EDGE IF RECEIVER
PROG.
FIR
(RCF)
FINE
DCC
BIST
SERIAL
PORT
SCLK
SDFS
SDO0
SDO1
DR
PROG.
FIR
(RCF)
FINE
DCC
BIST
MICRO
Figure 1.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2006–2007 Analog Devices, Inc. All rights reserved.






AD6650 Datasheet, Funktion
AD6650
ELECTRICAL CHARACTERISTICS
Table 3.
Parameter (Conditions)
LOGIC INPUTS
Logic Compatibility
Digital Logic
Logic 1 Voltage
Logic 0 Voltage
Logic 1 Current
Logic 0 Current
Input Capacitance
CLOCK INPUTS
Differential Input Voltage1
Common-Mode Input Voltage
Differential Input Resistance
Differential Input Capacitance
LOGIC OUTPUTS
Logic Compatibility
Logic 1 Voltage (IOH = 0.25 mA)
Logic 0 Voltage (IOL = 0.25 mA)
IDD SUPPLY CURRENT
CLK = 52 MHz (GSM Example)
IDVDD
IAVDD
POWER DISSIPATION
CLK = 52 MHz (GSM/EDGE Example)
Temp
Full
Full
Full
25°C
25°C
25°C
25°C
25°C
25°C
25°C
Full
Full
Full
Test Level
IV
IV
IV
V
V
V
V
V
V
V
IV
IV
Min Typ
3.3 V CMOS
2.0
0
60
7
5
0.4
DVDD/2
7.5
5
3.3 V CMOS/TTL
2.4 VDD − 0.2
0.2
Full VII
Full VII
Full VII
155
360
1.7
Max Unit
VDD V
0.8 V
μA
μA
pF
3.6 V p-p
V
pF
V
0.8 V
mA
mA
2.1 W
1 All ac specifications are tested by driving CLK and CLK differentially.
GENERAL TIMING CHARACTERISTICS
Table 4.
Parameter (Conditions)
CLK TIMING REQUIREMENTS
CLK Period1
CLK Width Low
CLK Width High
RESET TIMING REQUIREMENTS
RESET Width Low
PIN_SYNC TIMING REQUIREMENTS
SYNC to CLK Setup Time
SYNC to CLK Hold Time
SERIAL PORT TIMING REQUIREMENTS: SWITCHING CHARACTERISTICS2
CLK to SCLK Delay (Divide-by-1)
CLK to SCLK Delay (For Any Other Divisor)
CLK to SCLK Delay (Divide-by-2 or Even Number)
CLK to SCLK Delay (Divide-by-3 or Odd Number)
SCLK to SDFS Delay
SCLK to SDO0 Delay
SCLK to SDO1 Delay
SCLK to DR Delay
Symbol Temp Test Level Min Typ
Max Unit
tCLK
tCLKL
tCLKH
Full I
Full IV
Full IV
9.6 19.2 ns
0.5 × tCLK
ns
0.5 × tCLK
ns
tSSF Full IV
30
ns
tSS Full IV
tHS Full IV
−3
6
ns
ns
tDSCLK1 Full IV
tDSCLKH Full IV
tDSCLKL Full IV
tDSCLKLL Full IV
tDSDFS
Full IV
tDSDO0
Full IV
tDSDO1
Full IV
tDSDR
Full IV
3.2
4.4
4.7
4
1
0.5
0.5
1
12.5 ns
16 ns
16 ns
14 ns
2.6 ns
3.5 ns
3.5 ns
3.5 ns
1 Minimum specification is based on a 104 MSPS clock rate (an internal divide-by-2 must be used with a 104 MSPS clock rate); maximum specification is based on a
52 MSPS clock rate. This device is optimized to operate at a clock rate of 52 MSPS or 104 MSPS.
2 The timing parameters for SCLK, SDFS, SDO0, SDO1, and DR apply to both Channel 0 and Channel 1.
Rev. A | Page 5 of 44

6 Page









AD6650 pdf, datenblatt
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
A1 CORNER
INDEX AREA
1 2 3 4 5 6 7 8 9 10 11
A
B
C
D
E
F
G
H
J
K
L
AD6650
TOP VIEW
(Not to Scale)
Figure 14. Pin Configuration
AD6650
Table 8. Pin Configuration
12
A DGND
TDI
B SDFS
SCLK
C SDO1
SDO0
D D7
DR
E D5
D6
F D3
D4
G D1
D2
H DS (RD) D0
J R/W (WR) DTACK (RDY)
K A2
A1
L DGND
A0
12
3
TMS
TDO
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
CS
MODE2
3
4
TRST
TCLK
DVDD
DGND
DGND
DGND
DGND
DGND
DVDD
MODE1
MODE0
4
5
RESET
SYNC
DVDD
DGND
DGND
DGND
DGND
DGND
DVDD
CHIP_ID1
CHIP_ID0
5
6
DNC
DNC
DVDD
DGND
DGND
DGND
DGND
DGND
DVDD
DNC
DNC
6
7
AVDD
AVDD
AVDD
AVDD
AVDD
AVDD
AVDD
AVDD
AVDD
AVDD
AVDD
7
8
CLK
AVDD
AVDD
AVDD
AVDD
AVDD
AVDD
AVDD
AVDD
REFGND
VREF
8
9
CLK
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
REFT
REFB
9
10
AGND
AGND
AGND
AGND
AGND
DNC
AGND
AGND
AGND
AGND
AGND
10
11
AGND
BIN
BIN
AGND
LF
VLDO
CPOUT
AGND
AIN
AIN
AGND
11
A
B
C
D
E
F
G
H
J
K
L
Table 9. Pin Function Descriptions
Mnemonic
Type
POWER SUPPLY
DVDD
Power
AVDD
Power
DGND
Ground
AGND
Ground
DIGITAL INPUTS
RESET
Input
SYNC
Input
CHIP_ID[1:0]
Input
SERIAL DATA PORT
SCLK
Bidirectional
SDFS
Bidirectional
SDO[1:0]
Output
DR Output
MICROPORTCONTROL
D[7:0]
Bidirectional
A[2:0]
Input
CS Input
DS (RD)
Input
Description
3.3 V Digital Supply.
3.3 V Analog Supply.
Digital Ground.
Analog Ground.
Active Low Reset Pin.
Synchronizes Digital Filters.
Chip ID.
Serial Clock.
Serial Data Frame Sync.
Serial Data Outputs. Three-stated when inactive.
Output Data Ready Indicator.
Microport Data.
Microport Address Bits.
Chip Select.
Active Low Data Strobe (Active Low Read).
Rev. A | Page 11 of 44
No. of Pins
13
19
17
22
1
1
2
1
1
2
1
8
3
1
1

12 Page





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