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NHPXA270Cxxx Schematic ( PDF Datasheet ) - Intel

Teilenummer NHPXA270Cxxx
Beschreibung Microprocessor
Hersteller Intel
Logo Intel Logo 




Gesamt 70 Seiten
NHPXA270Cxxx Datasheet, Funktion
Intel® PXA270 Processor
Electrical, Mechanical, and Thermal Specification
Data Sheet
High-performance processor:
— Intel XScale® microarchitecture with
Intel® Wireless MMX™ Technology
— 7 Stage pipeline
— 32 KB instruction cache
— 32 KB data cache
— 2 KB “mini” data cache
— Extensive data buffering
256 Kbytes of internal SRAM for high
speed code or data storage preserved
during low-power states
High-speed baseband processor interface
(Mobile Scalable Link)
Rich serial peripheral set:
— AC’97 audio port
— I2S audio port
— USB Client controller
— USB Host controller
— USB On-The-Go controller
— Three high-speed UARTs (two with
hardware flow control)
— FIR and SIR infrared communications
port
Hardware debug features — IEEE JTAG
interface with boundary scan
Hardware performance-monitoring
features with on-chip trace buffer
Real-time clock
w Operating-system timers
w LCD Controller
w Universal Subscriber Identity Module
.DataSheet4U.cominterface
Low power:
— Wireless Intel Speedstep® Technology
— Less than 500 mW typical internal
dissipation
— Supply voltage may be reduced to
0.85 V
— Four low-power modes
— Dynamic voltage and frequency
management
High-performance memory controller:
— Four banks of SDRAM: up to 104 MHz
@ 2.5V, 3.0V, and 3.3V I/O interface
— Six static chip selects
— Support for PCMCIA and Compact
Flash
— Companion chip interface
Flexible clocking:
— CPU clock from 104 to 624 MHz
— Flexible memory clock ratios
— Frequency changes
— Functional clock gating
Additional peripherals for system
connectivity:
— SD Card / MMC Controller (with SPI
mode support)
— Memory Stick card controller
— Three SSP controllers
— Two I2C controllers
— Four pulse-width modulators (PWMs)
— Keypad interface with both direct and
matrix keys support
— Most peripheral pins double as GPIOs
Order Number 280002-005






NHPXA270Cxxx Datasheet, Funktion
Intel® PXA270 Processor
Contents
6-4 Hardware Reset Timing Specifications (OSCC[CRI] = 1) .................................6-5
6-5 GPIO Reset Timing Specifications .....................................................................6-6
6-6 Sleep-Mode Timing Specifications .....................................................................6-7
6-7 Deep-Sleep Mode Timing Specifications ...........................................................6-8
6-8 GPIO Pu/Pd Timing Specifications for Deep-Sleep Mode .................................6-9
6-9 Standby-Mode Timing Specifications ...............................................................6-10
6-10Idle-Mode Timing Specifications ......................................................................6-10
6-11Frequency-Change Timing Specifications .......................................................6-10
6-12Voltage-Change Timing Specification for a 1-Byte Command.........................6-11
6-13GPIO Timing Specifications .............................................................................6-11
6-14SRAM Read/Write AC Specification ................................................................6-12
6-15SDRAM Interface AC Specifications ................................................................6-13
6-16ROM AC Specification .....................................................................................6-18
6-17Synchronous Flash Read AC Specifications....................................................6-24
6-18Flash Memory AC Specification .......................................................................6-30
6-19SRAM Write AC Specification ..........................................................................6-34
6-20VLIO Timing .....................................................................................................6-37
6-21Expansion-Card Interface AC Specifications ...................................................6-40
6-22LCD Timing Specifications ...............................................................................6-43
6-23SSP Master Mode Timing Specifications .........................................................6-44
6-24Timing Specification SSP Slave Mode Transmitting Data to External
Peripheral .........................................................................................................6-45
6-25Timing Specification for SSP Slave Mode Receiving Data from External
Peripheral .........................................................................................................6-45
6-26Boundary Scan Timing Specifications..............................................................6-45
vi Electrical, Mechanical, and Thermal Specification

6 Page









NHPXA270Cxxx pdf, datenblatt
Intel® PXA270 Processor
Introduction
Single-bit items have either of two states:
clear — the item contains the value 0b0. To clear a bit, write 0b0 to it.
set — the item contains the value 0b1. To set a bit, write 0b1 to it.
1.1.3 Applicable Documents
Table 1-1 lists supplemental information sources for the PXA270 processor. Contact an Intel
representative for the latest document revisions and ordering instructions.
Table 1-1. Supplemental Documentation
Document Title
Intel® PXA27x Processor Family Developers Manual
ARM® Architecture Version 5T Specification (Document number ARM* DDI 0100D-10), and ARM®
Architecture Reference Manual (Document number ARM* DDI 0100B)
Intel® XScale™ Core Developer’s Manual
Intel® Wireless MMX™ Technology Developer’s Guide
Intel® PXA27x Processor Design Guide
Intel® PXA27x Processor Power Supply Requirements Application Note
§§
1-2 Electrical, Mechanical, and Thermal Specification

12 Page





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