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PDF MSM9005-xx Data sheet ( Hoja de datos )
| Número de pieza | MSM9005-xx | |
| Descripción | DOT MATRIX LCD CONTROLLER WITH 8-DOT COMMON DRIVER AND 65-DOT SEGMENT DRIVER | |
| Fabricantes | OKI electronic componets | |
| Logotipo |  |
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FEDL9005-03
FEDL9005-03
¡¡SemicondSucetormiconductor
MSM9005-xx
This versionM: SSMep9.020050-0xx
Previous version: Nov. 1997
DOT MATRIX LCD CONTROLLER WITH 8-DOT COMMON DRIVER AND 65-DOT SEGMENT
DRIVER
GENERAL DESCRIPTION
The MSM9005-xx is a controller/driver which displays 13 alphanumerics and symbols (5x7 dots)
and 65 arbitrators on a dot matrix LCD panel that has 8 common inputs and 65 segment inputs.
Command and display data are written by 8-bit serial transfer.
A maximum of 256 types of alphanumerics and symbols can be displayed using an internal
character display ROM. The character display ROM is reprogrammable. The general purpose
code is -01.
FEATURES
• Logic power supply (VDD)
• LCD bias power supply (VBI)
• LCD output resistance
: 2.5 to 5.5V
: 4.0 to 8.0V
Common driver (C1 to C8)
: 6 kW
Segment driver (S1 to S65)
: 18 kW
• Display content
Number of display characters
: 13 characters, 1 line
Arbitrator
: 65 dots
• Display control functions
Character blink
: Characters all on or all off can be selected
Arbitrator blink
: 1-dot unit or 5-dot units can be selected
All off setting possible
• 5 interfaces with microcomputer, CS, SI, SO, C/D and SHT (6 interfaces if RST is included)
• Internal character display ROM
: 5 ¥ 7 dots ¥ 256 types (reprogrammable)
• Internal oscillation circuit
: External R, C
• Package:
100-pin plastic QFP (QFP 100-P-1420-0.65-BK) (Product name: MSM9005-xxGS-BK)
xx indicates code number.
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1 page  
¡ Semiconductor
FEDL9005-03
MSM9005-xx
Pin Symbol Type Connected to
Description
36 VDD —
50 VSS
— These are power pins. Set VDD = 2.5 to 5.5V and VSS = 0V.
These are bias power pins for driving the LCD. Set the bias
voltage as follows.
35 VLCD1
4 V £ VDD – VLCD4 £ 8 V
34
VLCD2
—
33 VLCD3
31 VLCD4
—
VLCD1=VDD –
1
4
(VDD–VLCD4)
VLCD2=VDD –
2
4
(VDD–VLCD4)
VLCD3=VDD –
3
4
(VDD–VLCD4)
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¡ Semiconductor
FEDL9005-03
MSM9005-xx
Command Configuration
Command
Mnemonic Operation
1 LPA
Load Pointer
Address
2 DISP
DISPlay on/off
3 CHB
4 ABBC 1/5
CHaracter Blink
on/off
ArBitrator Blink
Control 1/5 dot
5 ABB
ArBitrator Blink
6 BPC
7 AINC
8 LOT
9 SOE/D
*: Don't care
Blink Pattern
Control
Address
INCrement
Load OpTion
Serial Out
Enable/Disable
MSB Input data LSB
D7 D6 D5 D4 D3 D2 D1 D0
Comment
1 1 * A4 A3 A2 A1 A0 Sets address pointer value
A0, A1, A2, A3 A4: address pointer value
(binary)
Sets on/off of LCD panel
1 0 0 * 1 0 0 DI
Panel is on when DI = "1"
Panel is off when DI = "0"
Sets blink in 5 dot units
0 * * * 0 0 CB * Blink starts in 5 dot units when CB = "1"
Blink is cleared when CB = "0"
Sets writing method to arbitrator blink RAM
1 0 0 1 1 1 0 BC Writing in 1 dot unit is enabled when BC = "1"
Writing in 5 dot unit is enabled when BC = "0"
Sets start/stop of writing to arbitrator blink RAM
1 0 0 0 1 1 0 AB Writing in 1 dot unit starts when AB = "1"
Writing in 1 dot unit stops when AB = "0"
Sets blink pattern of characters
1 0 0 * 0 0 1 BP When BP = 1, all off ´ character blink
When BP = 0, all on ´ character blink
1 0 0 * 1 * 1 * Increments address pointer value by 1
1 0 1 1 * * I1 I0 Sets additional function of AINC command
Set SO pin
1 0 0 * 0 1 1 S SO pin is a CMOS output when S = "1"
SO pin is in a high impedance state when S = "0"
The commands listed above requires the wait time (21 ¥ 1/fOSC).
The address pointer value is incremented by 1 when CG ROM code data, arbitrator display data
and arbitrator blink data are input and when AINC and CHB commands are executed.
11/30
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| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet MSM9005-xx.PDF ] | |
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