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WEDPN4M64V Schematic ( PDF Datasheet ) - White Electronic Designs

Teilenummer WEDPN4M64V
Beschreibung 4M x 64 SDRAM
Hersteller White Electronic Designs
Logo White Electronic Designs Logo 




Gesamt 12 Seiten
WEDPN4M64V Datasheet, Funktion
White Electronic Designs
WEDPN4M64V-XBX
4Mx64 Synchronous DRAM
FEATURES
GENERAL DESCRIPTION
High Frequency = 100, 125, 133MHz
Package:
• 219 Plastic Ball Grid Array (PBGA), 21 x 21mm
Single 3.3V ±0.3V power supply
Fully Synchronous; all signals registered on positive
edge of system clock cycle
Internal pipelined operation; column address can be
changed every clock cycle
Internal banks for hiding row access/precharge
Programmable Burst length 1,2,4,8 or full page
4096 refresh cycles
Commercial, Industrial and Military Temperature
Ranges
Organized as 4M x 64
The 32MByte (256Mb) SDRAM is a high-speed CMOS,
dynamic random-access ,memory using 4 chips containing
67,108,864 bits. Each chip is internally configured as a
quad-bank DRAM with a synchronous interface. Each of the
chip’s 16,777,216-bit banks is organized as 4,096 rows by
256 columns by 16 bits.
Read and write accesses to the SDRAM are burst oriented;
accesses start at a selected location and continue for
a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an ACTIVE
command, which is then followed by a READ or WRITE
command. The address bits registered coincident with the
ACTIVE command are used to select the bank and row to
be accessed (BA0, BA1 select the bank; A0-11 select the
row). The address bits registered coincident with the READ
or WRITE command are used to select the starting column
location for the burst access.
• User Configurable as 2x4Mx32 or 4x4Mx16
The SDRAM provides for programmable READ or WRITE
Weight: WEDPN4M64V-XBX - 2 grams typical
burst lengths of 1, 2, 4 or 8 locations, or the full page, with
a burst terminate option. An AUTO PRECHARGE function
BENEFITS
may be enabled to provide a self-timed row precharge that
is initiated at the end of the burst sequence.
58% SPACE SAVINGS
Reduced part count
w Reduced trace lengths for lower parasitic
w capacitance
wLaminate interposer for optimum TCE match
Suitable for hi-reliability applications
.DUpgradeable to 8M x 64 (contact factory for
availability)
ata*This product is subject to change without notice.
The 256Mb SDRAM uses an internal pipelined architecture to
achieve high-speed operation. This architecture is compatible
with the 2n rule of prefetch architectures, but it also allows
the column address to be changed on every clock cycle to
achieve a high-speed, fully random access. Precharging one
bank while accessing one of the other three banks will hide
the precharge cycles and provide seamless, high-speed,
random-access operation.
The 256Mb SDRAM is designed to operate in 3.3V, low-
power memory systems. An auto refresh mode is provided,
along with a power-saving, power-down mode.
Sh Discrete Approach
11.9
eet54
422.3 TSOP
54
TSOP
54
TSOP
54
TSOP
U.cArea
4 x 265mm2 = 1061mm2
ACTUAL SIZE
WEDPN4M64V-XBX
21
21
S
A
V
I
N
G
S
441mm2 58%
omWhite Electronic Designs Corp. reserves the right to change products or specifications without notice.
January 2005
Rev. 8
1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com






WEDPN4M64V Datasheet, Funktion
White Electronic Designs
WEDPN4M64V-XBX
CK
COMMAND
I/O
FIGURE 3 – CAS LATENCY
T0 T1 T2 T3
READ
NOP
tLZ
tAC
CAS Latency = 2
NOP
tOH
DOUT
DON’T CARE
UNDEFINED
CK
COMMAND
T0
READ
I/O
T1 T2 T3 T4
NOP
NOP
tLZ
tAC
CAS Latency = 3
NOP
tOH
DOUT
BURST TYPE
Accesses within a given burst may be programmed to be
either sequential or interleaved; this is referred to as the
burst type and is selected via bit M3.
The ordering of accesses within a burst is determined by
the burst length, the burst type and the starting column
address, as shown in Table 1.
CAS LATENCY
The CAS latency is the delay, in clock cycles, between the
registration of a READ command and the availability of the
first piece of output data. The latency can be set to two or
three clocks.
If a READ command is registered at clock edge n, and
the latency is m clocks, the data will be available by clock
edge n+m. The I/Os will start driving as a result of the clock
edge one cycle earlier (n + m - 1), and provided that the
relevant access times are met, the data will be valid by
clock edge n + m. For example, assuming that the clock
cycle time is such that all relevant access times are met,
if a READ command is registered at T0 and the latency is
programmed to two clocks, the I/Os will start driving after
T1 and the data will be valid by T2. Table 2 below indicates
the operating frequencies at which each CAS latency setting
can be used.
Reserved states should not be used as unknown operation
or incompatibility with future versions may result.
OPERATING MODE
The normal operating mode is selected by setting M7and M8
to zero; the other combinations of values for M7 and M8 are
reserved for future use and/or test modes. The programmed
burst length applies to both READ and WRITE bursts.
Test modes and reserved states should not be used
because unknown operation or incompatibility with future
versions may result.
WRITE BURST MODE
When M9 = 0, the burst length programmed via M0-M2
applies to both READ and WRITE bursts; when M9 = 1, the
programmed burst length applies to READ bursts, but write
accesses are single-location (nonburst) accesses.
TABLE 2 – CAS LATENCY
SPEED
-100
-125
-133
ALLOWABLE OPERATING
FREQUENCY (MHz)
CAS LATENCY = 2
≤ 75
≤ 100
≤ 100
CAS LATENCY = 3
≤ 100
≤ 125
≤ 133
COMMANDS
The Truth Table provides a quick reference of available
commands. This is followed by a written description of each
command. Three additional Truth Tables appear following
the Operation section; these tables provide current state/
next state information.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
January 2005
Rev. 8
6 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

6 Page









WEDPN4M64V pdf, datenblatt
White Electronic Designs
WEDPN4M64V-XBX
PACKAGE 739: 219 PLASTIC BALL GRID ARRAY (PBGA)
19.05 (0.750)
NOM
1.27 (0.050)
NOM
Bottom View
21.1 (0.831) SQ. MAX
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
219 x Ø 0.762 (0.030) NOM
19.05 (0.750) NOM
2.03 (0.080)
MAX
0.61
(0.024)
NOM
ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES
ORDERING INFORMATION
WED P N 4M 64 V - XXX B X
DEVICE GRADE:
M = Military
-55°C to +125°C
I = Industrial -40°C to +85°C
C = Commercial 0°C to +70°C
PACKAGE:
B = 219 Plastic Ball Grid Array (PBGA), 21mm x 21mm
FREQUENCY (MHz)
100 = 100MHz
125 = 125MHz
133 = 133MHz
3.3V Power Supply
CONFIGURATION, 4M x 64
SDRAM
PLASTIC
WHITE ELECTRONIC DESIGNS CORP.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
January 2005
Rev. 8
12 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

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