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M30302MEP-xxx Schematic ( PDF Datasheet ) - Renesas Technology

Teilenummer M30302MEP-xxx
Beschreibung (M30302Mx) Single-Chip 16-Bit CMOS Microcomputer
Hersteller Renesas Technology
Logo Renesas Technology Logo 




Gesamt 30 Seiten
M30302MEP-xxx Datasheet, Funktion
M16C/30P Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
REJ03B0088-0080
Rev.0.80
Mar 18, 2005
1. Overview
The M16C/30P Group of single-chip microcomputers are built using the high-performance silicon gate CMOS process
using a M16C/60 Series CPU core and are packaged in a 100-pin plastic molded QFP.
These single-chip microcomputers operate using sophisticated instructions featuring a high level of instruction
efficiency. With 1M bytes of address space, they are capable of executing instructions at high speed. In addition, this
microcomputer contains a multiplier and DMAC which combined with fast instruction processing capability, makes it
suitable for control of various OA, communication, and industrial equipment which requires high-speed arithmetic/
logic operations.
1.1 Applications
Audio, cameras, TV, home appliance, office/communications/portable/industrial equipment, etc.
Specifications written in this manual are believed to be accurate,
but are not guaranteed to be entirely free of error. Specifications in
this manual may be changed for functional or performance
improvements. Please make sure your manual is the latest edition.
Rev.0.80 Mar 18, 2005 Page 1 of 34
REJ03B0088-0080






M30302MEP-xxx Datasheet, Funktion
Under development Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/30P Group
PIN CONFIGURATION (top view)
1. Overview
P1_2
P1_1
P1_0
P0_7/AN0_7
P0_6/AN0_6
P0_5/AN0_5
P0_4/AN0_4
P0_3/AN0_3
P0_2/AN0_2
P0_1/AN0_1
P0_0/AN0_0
P10_7/AN7/KI3
P10_6/AN6/KI2
P10_5/AN5/KI1
P10_4/AN4/KI0
P10_3/AN3
P10_2/AN2
P10_1/AN1
AVSS
P10_0/AN0
VREF
AVCC
P9_7/ADTRG
P9_6/ANEX1
P9_5/ANEX0
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
76
77
78
79
80
81
82
83
84
85
86
87
88 M16C/30P Group
89
90
91
92
93
94
95
96
97
98
99
100
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
P4_2
P4_3
P4_4
P4_5
P4_6
P4_7
P5_0
P5_1
P5_2
P5_3
P5_4
P5_5
P5_6
P5_7/CLKOUT
P6_0/CTS0/RTS0
P6_1/CLK0
P6_2/RXD0/SCL0
P6_3/TXD0/SDA0
P6_4/CTS1/RTS1/CTS0/CLKS1
P6_5/CLK1
P6_6/RXD1/SCL1
P6_7/TXD1/SDA1
P7_0/TXD2/SDA2/TA0OUT(1)
P7_1/RXD2/SCL2/TA0IN(1)
P7_2/CLK2/TA1OUT
NOTES:
1. P7_0 and P7_1 are N channel open-drain output pins.
2. Use the M16C/30P on VCC1=VCC2.
Figure 1.4 Pin Configuration (Top View)
Package : 100P6Q-A
Rev.0.80 Mar 18, 2005 Page 6 of 34
REJ03B0088-0080

6 Page









M30302MEP-xxx pdf, datenblatt
Under development Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/30P Group
3. Memory
3. Memory
Figure 3.1 is a Memory Map of the M16C/30P group. The address space extends the 1M bytes from address 00000h to
FFFFFh.
The internal ROM is allocated in a lower address direction beginning with address FFFFFh. For example, a 64-Kbyte
internal ROM is allocated to the addresses from F0000h to FFFFFh.
The fixed interrupt vector table is allocated to the addresses from FFFDCh to FFFFFh. Therefore, store the start
address of each interrupt routine here.
The internal RAM is allocated in an upper address direction beginning with address 00400h. For example, a 10-Kbyte
internal RAM is allocated to the addresses from 00400h to 02BFFh. In addition to storing data, the internal RAM also
stores the stack used when calling subroutines and when interrupts are generated. The SFR is allocated to the addresses
from 00000h to 003FFh. Peripheral function control registers are located here. Of the SFR, any area which has no
functions allocated is reserved for future use and cannot be used by users.
The special page vector table is allocated to the addresses from FFE00h to FFFDBh. This vector is used by the JMPS
or JSRS instruction. For details, refer to the M16C/60 and M16C/20 Series Software Manual.
00000h
00400h
XXXXXh
SFR
Internal RAM
Reserved area
Internal RAM
Internal ROM
Size Address XXXXXh Size Address YYYYYh
5 kbytes
017FFh 96 kbytes E8000h
6 kbytes 01BFFh 128 kbytes E0000h
192 kbytes D0000h
YYYYYh
FFFFFh
Internal ROM
FFE00h
Special page
vector table
FFFDCh
FFFFFh
Undefined instruction
Overflow
BRK instruction
Address match
Single step
Watchdog timer
DBC
NMI
Reset
Figure 3.1 Memory Map
Rev.0.80 Mar 18, 2005 Page 12 of 34
REJ03B0088-0080

12 Page





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