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MK1493-02A Schematic ( PDF Datasheet ) - Integrated Circuit System

Teilenummer MK1493-02A
Beschreibung Networking/pci Clock Generator
Hersteller Integrated Circuit System
Logo Integrated Circuit System Logo 




Gesamt 24 Seiten
MK1493-02A Datasheet, Funktion
MK1493-02A
Networking/PCI Clock Generator
Description
The MK1493-02A is a general purpose clock generator
that provides an integrated clocking solution for
PCI/Networking applications. It provides two pairs of
differential CPU clocks, four PCI clocks, seven PCI_X
clocks, two reference clocks, additional clock selectable
from REF/50 MHz, and six pairs of SSTL2 DDR at
2.5 V. All complementary outputs operate only from
a 2.5 V power supply.
Input/Output Features
Packaged in 56-pin TSSOP package
2 - Pairs of differential CPU clocks (differential
current mode)
4 - PCI @ 3.3 V
7 - PCI_X @ 3.3 V
2 - REF @ 3.3 V, Fixed
6 - Pairs of differential SSTL2 DDR @ 2.5 V
1 - REF/50 MHz, selectable
Spread spectrum for EMI control
Supports SMBUS index read/write and blocks
read/write operations
Uses external 25 or 50 MHz crystal or clock
CPU output jitter <125 ps
PCI cycle to cycle output jitter <250 ps
DDR cycle to cycle output jitter <150 ps
Block Diagram
PLL2
50MHz/REF2
X1
External capacitor
required with crystal for
accurate timing of clock
XTAL
OSC
2 REF(0:1)
X2
PLL1
Spread
Spectrum
ww OE
w FREQSEL
FS (3:0)
.D SDATA
SCLK
a CLK_STOPB
ta PCI_STOPB
S SSEN
4
Control
Logic
Config.
Reg.
CPU
Divider
PCI
Divider
Stop
Stop
Delay
Delay
AGP
Divider
DDR
Divider
Stop
Stop
Delay
Delay
2
2
CPUCLKT (1:0)
CPUCLKC (1:0)
7 PCI_XCLK (6:0)
4 PCI (3:0)
6
6
DDRT (5:0)
DDRC (5:0)
IREF
heet4UMDS 1493-02A C
1
Revision 020204
.comIntegrated Circuit Systems, Inc. 525 Race Street, San Jose, CA 95126 tel (408) 297-1201 www.icst.com






MK1493-02A Datasheet, Funktion
MK1493-02A
Networking/PCI Clock Generator
Serial Configuration Command Bitmap Byte 0: Functionary and frequency select register (default = 0)
Bit Description
SSEN FS3
FS2
FS1
FS0
CPUCLK DDR
(MHz) (MHz)
PCI
(MHz)
PCI_X
F in
Bit2 Bit7 Bit6 Bit5 Bit4
0 0000
Reserved
0 0001
Reserved
0 0010
Reserved
0 0011
Reserved
0 0 1 0 0 33 33 33 33 50
0 0 1 0 1 100 133 33 33 50
0 0 1 1 0 33 33 33 33 25
0 0 1 1 1 33 33 33 133 25
0 1 0 0 0 100 200 66 33 25
0 1 0 0 1 200 200 66 33 25
0 1 0 1 0 133 133 33 66 25
0 1 0 1 1 133 133 33 33 25
0 1 1 0 0 133 133 66 66 25
0 1 1 0 1 150 150 33 33 25
0 1 1 1 0 125 125 33 33 25
0 1 1 1 1 166 166 33 33 25
1 0000
Reserved
1 0001
Reserved
1 0010
Reserved
1 0011
Reserved
1 0 1 0 0 33 33 33 33 50
1 0 1 0 1 100 133 33 33 50
1 0 1 1 0 33 33 33 33 25
1 0 1 1 1 33 33 33 133 25
1 1 0 0 0 100 200 66 33 25
1 1 0 0 1 200 200 66 33 25
1 1 0 1 0 133 133 33 66 25
1 1 0 1 1 133 133 33 33 25
1 1 1 0 0 133 133 66 66 25
1 1 1 0 1 150 150 33 33 25
1 1 1 1 0 125 125 33 33 25
1 1 1 1 1 166 166 33 33 25
Bit3
0 - Frequency is selected by hardware select, Latched inputs
1 - Frequency is selected by Bit 2, 7:4
DDR
Diff
Out
N
N
N
N
N
N
N
N
Y
Y
Y
Y
Y
Y
Y
Y
N
N
N
N
N
N
N
N
Y
Y
Y
Y
Y
Y
Y
Y
Spread Percentage Power up
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
(1% down spread)
(1% down spread)
(1% down spread)
(1% down spread)
(1% down spread)
(1% down spread)
(1% down spread)
(1% down spread)
(1% down spread)
(1% down spread)
(1% down spread)
(1% down spread)
(1% down spread)
(1% down spread)
(1% down spread)
(1% down spread)
Default
Bit 1 RESERVED
Bit 0
0 - Running
1 - Tristate all outputs
MDS 1493-02A C
6
Revision 020204
Integrated Circuit Systems, Inc. 525 Race Street, San Jose, CA 95126 tel (408) 297-1201 www.icst.com

6 Page









MK1493-02A pdf, datenblatt
MK1493-02A
Networking/PCI Clock Generator
Byte 16: Output Divider Control Register
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
PCI Div 3
PCI Div 2
PCI Div 1
PCI Div 0
PUP
X
X
X
X
X
X
X
X
Description
PCI clock divider ratio can be configured via these
four bits individually. For divider selection table, refer
to Table 2. Default at power up is latched FS divider.
RESERVED
Byte 17: Output Divider Control Register
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
PCI_XINV
PCI_INV
DDR_INV
CPU_INV
PCI _XDiv 3
PCI _XDiv 2
PCI _XDiv 1
PCI_X Div 0
PUP
X
X
X
X
X
X
X
X
Description
PCI_X Phase Inversion bit
PCI Phase Inversion bit
DDR Phase Inversion bit
CPUCLK Phase Inversion bit
PCI clock divider ratio can be configured via these
Table 1 CPU/DDR Output Divide
Div (3:2)
Div (1:0)
00
01
10
00 /2 /4 /8
01 /3 /6 /12
10 /5 /10 /20
11 /9 /18 /36
11
/16
/24
/40
/72
Table 2 PCI/PCI_X Output Divide
Div (3:2)
Div (1:0)
00
01
10
00 /2 /4 /8
01 /3 /6 /12
10 /9 /18 /36
11 /15 /30 /60
11
/16
/24
/72
/120
MDS 1493-02A C
12
Revision 020204
Integrated Circuit Systems, Inc. 525 Race Street, San Jose, CA 95126 tel (408) 297-1201 www.icst.com

12 Page





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