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AD8317 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD8317
Beschreibung Log Detector / Controller
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 21 Seiten
AD8317 Datasheet, Funktion
FEATURES
Wide bandwidth: 1 MHz to 10 GHz
High accuracy: ±1.0 dB over temperature
55 dB dynamic range up to 8 GHz ± 3 dB error
Stability over temperature: ±0.5 dB
Low noise measurement/controller output, VOUT
Pulse response time: 6 ns/10 ns (fall/rise)
Small footprint, 2 mm × 3 mm LFCSP
Supply operation: 3.0 V to 5.5 V @ 22 mA
Fabricated using high speed SiGe process
APPLICATIONS
RF transmitter PA setpoint control and level monitoring
Power monitoring in radio link transmitters
RSSI measurement in base stations, WLANs, WiMAX, and radars
GENERAL DESCRIPTION
The AD8317 is a demodulating logarithmic amplifier, capable
of accurately converting an RF input signal to a corresponding
decibel-scaled output. It employs the progressive compression
technique over a cascaded amplifier chain, each stage of which
is equipped with a detector cell. The device can be used in either
measurement or controller modes. The AD8317 maintains
accurate log conformance for signals of 1 MHz to 8 GHz and
provides useful operation to 10 GHz. The input dynamic range
is typically 55 dB (re: 50 Ω) with less than ±3 dB error. The
AD8317 has 6 ns/10 ns response time (fall time/rise time) that
enables RF burst detection to a pulse rate of beyond 50 MHz.
The device provides unprecedented logarithmic intercept stability
vs. ambient temperature conditions. A supply of 3.0 V to 5.5 V
is required to power the device. Current consumption is typically
22 mA, and it decreases to 200 μA when the device is disabled.
The AD8317 can be configured to provide a control voltage to a
power amplifier or a measurement output from the VOUT pin.
Because the output can be used for controller applications, special
attention has been paid to minimize wideband noise. In this
mode, the setpoint control voltage is applied to the VSET pin.
1 MHz to 10 GHz, 55 dB
Log Detector/Controller
AD8317
FUNCTIONAL BLOCK DIAGRAM
VPOS
TADJ
GAIN
BIAS
SLOPE
IV
VSET
INHI
INLO
DET
DET
DET
DET
COMM
Figure 1.
IV
VOUT
CLPF
The feedback loop through an RF amplifier is closed via VOUT,
the output of which regulates the output of the amplifier to a
magnitude corresponding to VSET. The AD8317 provides 0 V to
(VPOS − 0.1 V) output capability at the VOUT pin, suitable for
controller applications. As a measurement device, VOUT is
externally connected to VSET to produce an output voltage,
VOUT, that is a decreasing linear-in-dB function of the RF input
signal amplitude.
The logarithmic slope is 22 mV/dB, determined by the VSET
interface. The intercept is 15 dBm (re: 50 Ω, CW input) using
the INHI input. These parameters are very stable against supply
and temperature variations.
The AD8317 is fabricated on a SiGe bipolar IC process and is
available in a 2 mm × 3 mm, 8-lead LFCSP with an operating
temperature range of −40°C to +85°C.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2005–2008 Analog Devices, Inc. All rights reserved.






AD8317 Datasheet, Funktion
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter
Supply Voltage, VPOS
VSET Voltage
Input Power (Single-Ended, Re: 50 Ω)
Internal Power Dissipation
θJA
Maximum Junction Temperature
Operating Temperature Range
Storage Temperature Range
Lead Temperature (Soldering, 60 sec)
Rating
5.7 V
0 V to VPOS
12 dBm
0.73 W
55°C/W
125°C
−40°C to +85°C
−65°C to +150°C
260°C
AD8317
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
Rev. B | Page 5 of 20

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AD8317 pdf, datenblatt
AD8317
USING THE AD8317
BASIC CONNECTIONS
The AD8317 is specified for operation up to 10 GHz; as a result,
low impedance supply pins with adequate isolation between
functions are essential. A power supply voltage of between 3.0 V
and 5.5 V should be applied to VPOS. Power supply decoupling
capacitors of 100 pF and 0.1 μF should be connected close to
this power supply pin.
VS (3.0V TO 5.5V)
C5
0.1µF R2
C4 0
SIGNAL
INPUT
100pF
C2
1
R1
52.3
47nF
C1
8
INLO
INHI
1
7
VPOS
6
TADJ
AD8317
COMM CLPF
23
5
VOUT
VSET
4
47nF
2
VOUT
R4
0
1SEE THE TEMPERATURE COMPENSATION OF OUTPUT VOLTAGE SECTION.
2SEE THE OUTPUT FILTERING SECTION.
Figure 22. Basic Connections
The paddle of the LFCSP package is internally connected to
COMM. For optimum thermal and electrical performance, the
paddle should be soldered to a low impedance ground plane.
INPUT SIGNAL COUPLING
The RF input (INHI) is single-ended and must be ac-coupled.
INLO (input common) should be ac-coupled to ground.
Suggested coupling capacitors are 47 nF ceramic 0402-style
capacitors for input frequencies of 1 MHz to 10 GHz. The
coupling capacitors should be mounted close to the INHI and
INLO pins. The coupling capacitor values can be increased to
lower the high-pass cutoff frequency of the input stage. The
high-pass corner is set by the input coupling capacitors and the
internal 10 pF high-pass capacitor. The dc voltage on INHI and
INLO is approximately one diode voltage drop below VPOS.
VPOS
5pF
CURRENT
5pF
18.7k
INHI
INLO
18.7k
FIRST
GAIN
STAGE
2kA = 9dB
gm
STAGE
Figure 23. Input Interface
OFFSET
COMP
Figure 22) combines with the relatively high input impedance to
give an adequate broadband 50 Ω match.
The coupling time constant, 50 × CC/2, forms a high-pass
corner with a 3 dB attenuation at fHP = 1/(2π × 50 × CC ), where
C1 = C2 = CC. Using the typical value of 47 nF, this high-pass
corner is ~68 kHz. In high frequency applications, fHP should be
as large as possible to minimize the coupling of unwanted low
frequency signals. In low frequency applications, a simple RC
network forming a low-pass filter should be added at the input
for similar reasons. This low-pass filter network should generally
be placed at the generator side of the coupling capacitors, thereby
lowering the required capacitance value for a given high-pass
corner frequency.
OUTPUT INTERFACE
The VOUT pin is driven by a PNP output stage. An internal
10 Ω resistor is placed in series with the output and the VOUT
pin. The rise time of the output is limited mainly by the slew
on CLPF. The fall time is an RC-limited slew given by the load
capacitance and the pull-down resistance at VOUT. There is an
internal pull-down resistor of 1.6 kΩ. A resistive load at VOUT
is placed in parallel with the internal pull-down resistor to
provide additional discharge current.
VPOS
CLPF
+
0.8V
10
VOUT
1200
COMM
400
Figure 24. Output Interface
To reduce the fall time, VOUT should be loaded with a resistive
load of <1.6 kΩ. For example, with an external load of 150 Ω,
the AD8317 fall time is <7 ns.
SETPOINT INTERFACE
The VSET input drives the high impedance (40 kΩ) input of an
internal op amp. The VSET voltage appears across the internal
1.5 kΩ resistor to generate ISET. When a portion of VOUT is
applied to VSET, the feedback loop forces
−ID × log10(VIN/VINTERCEPT) = ISET
If VSET = VOUT/2x, then ISET = VOUT/(2x × 1.5 kΩ).
(2)
The result is
VOUT = (−ID × 1.5 kΩ × 2x) × log10(VIN/VINTERCEPT)
VSET
20kVSET
ISET
While the input can be reactively matched, in general, this is not
necessary. An external 52.3 Ω shunt resistor (connected on the
signal side of the input coupling capacitors, as shown in
20k
COMM
1.5k
COMM
Rev. B | Page 11 of 20
Figure 25. VSET Interface

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