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UDA1380 Schematic ( PDF Datasheet ) - Integrated Circuit Systems

Teilenummer UDA1380
Beschreibung Stereo audio coder-decoder for MD / CD and MP3
Hersteller Integrated Circuit Systems
Logo Integrated Circuit Systems Logo 




Gesamt 30 Seiten
UDA1380 Datasheet, Funktion
INTEGRATED CIRCUITS
DATA SHEET
UDA1380
Stereo audio coder-decoder
for MD, CD and MP3
Product specification
2002 Sep 16






UDA1380 Datasheet, Funktion
Philips Semiconductors
Stereo audio coder-decoder
for MD, CD and MP3
Product specification
UDA1380
SYMBOL
PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
Analog-to-digital converter (supply voltage 3.0 V)
Do
(THD+N)/S48
S/N48
αcs
digital output level
total harmonic distortion-
plus-noise to signal ratio at
fs = 48 kHz
signal-to-noise ratio at
fs = 48 kHz
channel separation
at 0 dB setting; Vi(rms) = 1.0 V
at 1 dBFS
at 60 dBFS; A-weighted
Vi = 0 V; A-weighted
− −1
− −85
− −37
97
100
LNA input plus analog-to-digital converter (supply voltage 3.0 V)
Vi(rms)
input voltage (RMS value)
at 0 dBFS digital output; 2.2 k
source impedance
−−
(THD+N)/S48
S/N48
αcs
total harmonic
distortion-plus-noise to
signal ratio at fs = 48 kHz
signal-to-noise ratio at
fs = 48 kHz
channel separation
at 0 dB
at 60 dB; A-weighted
Vi = 0 V; A-weighted
− −74
− −25
85
70
Digital-to-analog converter (supply voltage 3.0 V)
Vo(rms)
(THD+N)/S48
(THD+N)/S96
S/N48
S/N96
αcs
output voltage (RMS value)
total harmonic
distortion-plus-noise to
signal ratio at fs = 48 kHz
total harmonic
distortion-plus-noise to
signal ratio at fs = 96 kHz
signal-to-noise ratio at
fs = 48 kHz
signal-to-noise ratio at
fs = 96 kHz
channel separation
at 0 dBFS digital input; note 1
at 0 dB
at 60 dB; A-weighted
at 0 dB
at 60 dB; A-weighted
code = 0; A-weighted
code = 0; A-weighted
0.9
− −88
− −40
− −80
− −37
100
97
90
AVC (line input via ADC input; output on line output and headphone driver; supply voltage 3.0 V)
Vi(rms)
(THD+N)/S48
S/N48
input voltage (RMS value)
total harmonic
distortion-plus-noise to
signal ratio at fs = 48 kHz
signal-to-noise ratio at
fs = 48 kHz
at 0 dB
at 60 dB; A-weighted
Vi = 0 V; A-weighted
150
− −80
− −28
87
35
dBFS
dB
dB
dB
dB
mV
dB
dB
dB
dB
V
dB
dB
dB
dB
dB
dB
dB
mV
dB
dB
dB
2002 Sep 16
6

6 Page









UDA1380 pdf, datenblatt
Philips Semiconductors
Stereo audio coder-decoder
for MD, CD and MP3
Product specification
UDA1380
8.1.2 CLOCK DISTRIBUTION
Figure 5 shows the main clock distribution for the SYSCLK domain and the WSPLL clock domain.
For power saving reasons each clock signal inside the system must be controlled and enabled via a separate bit in the
L3-bus and I2C-bus registers (ADC_CLK).
The DAC part of the UDA1380 can operate from 8 to 100 kHz sampling frequency (fs). This applies to the DAC part only;
the ADC part can run from 8 to 55 kHz.
handbook, full pagewidth
SYSCLK
WSI
enable clock
256/384/512/768fs
CLK_DIV
128fs
ADC_CLK
128fs
enable
clock
256fs
WSPLL
128fs
enable
clock
128fs
DAC_CLK
ADC
DECIMATOR
L3 or I2C-BUS
REGISTER
DECIMATOR
I2S-BUS
OUTPUT BLOCK
I2S-BUS
INPUT BLOCK
L3 or I2C-BUS
REGISTER
INTERPOLATOR
INTERPOLATOR
FSDAC
enable clock
MGU528
Fig.5 Clock routing for the main blocks inside the coder-decoder.
2002 Sep 16
12

12 Page





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