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PDF MC145151-2 Data sheet ( Hoja de datos )
| Número de pieza | MC145151-2 | |
| Descripción | (MC145151-2 - MC145158-2) Parallel-Input PLL Frequency Synthesizer | |
| Fabricantes | Motorola Semiconductors | |
| Logotipo |  |
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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order this document
by MC145151–2/D
PLL Frequency Synthesizer
Family
CMOS
The devices described in this document are typically used as low–power,
phase–locked loop frequency synthesizers. When combined with an external
low–pass filter and voltage–controlled oscillator, these devices can provide all
the remaining functions for a PLL frequency synthesizer operating up to the
device’s frequency limit. For higher VCO frequency operation, a down mixer or
a prescaler can be used between the VCO and the synthesizer IC.
These frequency synthesizer chips can be found in the following and other
applications:
CATV
AM/FM Radios
Two–Way Radios
TV Tuning
Scanning Receivers
Amateur Radio
OSC ÷ R
MC145151-2
MC145152-2
MC145155-2
MC145156-2
MC145157-2
MC145158-2
CONTROL LOGIC
φ
÷A ÷N
÷ P/P + 1
VCO
OUTPUT
FREQUENCY
DEVICE DETAIL SHEETS
CONTENTS
Page
MC145151–2 Parallel–Input, Single–Modulus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
MC145152–2 Parallel–Input, Dual–Modulus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
MC145155–2 Serial–Input, Single–Modulus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
MC145156–2 Serial–Input, Dual–Modulus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
MC145157–2 Serial–Input, Single–Modulus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
MC145158–2 Serial–Input, Dual–Modulus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
FAMILY CHARACTERISTICS
Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Frequency Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Phase Detector/Lock Detector Output Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
DESIGN CONSIDERATIONS
Phase–Locked Loop — Low–Pass Filter Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Crystal Oscillator Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Dual–Modulus Prescaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
REV 1
8/95
©MOMoTtoOroRla,OInLc.A1995
MC145151–2 through MC145158–2
1
1 page  
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Parallel-Input PLL Frequency
Synthesizer
Interfaces with Dual–Modulus Prescalers
The MC145152–2 is programmed by sixteen parallel inputs for the N and A
counters and three input lines for the R counter. The device features consist of
a reference oscillator, selectable–reference divider, two–output phase detector,
10–bit programmable divide–by–N counter, and 6–bit programmable ÷ A
counter.
The MC145152–2 is an improved–performance drop–in replacement for the
MC145152–1. Power consumption has decreased and ESD and latch–up
performance have improved.
• Operating Temperature Range: – 40 to 85°C
• Low Power Consumption Through Use of CMOS Technology
• 3.0 to 9.0 V Supply Range
• On– or Off–Chip Reference Oscillator Operation
• Lock Detect Signal
• Dual Modulus/Parallel Programming
• 8 User–Selectable ÷ R Values: 8, 64, 128, 256, 512, 1024, 1160, 2048
• ÷ N Range = 3 to 1023, ÷ A Range = 0 to 63
• Chip Complexity: 8000 FETs or 2000 Equivalent Gates
• See Application Note AN980
MC145152-2
28
1
P SUFFIX
PLASTIC DIP
CASE 710
28
1
DW SUFFIX
SOG PACKAGE
CASE 751F
ORDERING INFORMATION
MC145152P2 Plastic DIP
MC145152DW2 SOG Package
PIN ASSIGNMENT
fin 1
VSS 2
VDD 3
RA0 4
RA1 5
RA2 6
φR 7
φV 8
MC 9
A5 10
N0 11
N1 12
N2 13
N3 14
28 LD
27 OSCin
26 OSCout
25 A4
24 A3
23 A0
22 A2
21 A1
20 N9
19 N8
18 N7
17 N6
16 N5
15 N4
REV 1
8/95
©MOMoTtoOroRla,OInLc.A1995
MC145151–2 through MC145158–2
5
5 Page 
OUTPUT PINS
PDout
Phase Detector A Output (PDIP, SOG – Pin 6)
Three–state output of phase detector for use as loop error
signal. Double–ended outputs are also available for this pur-
pose (see φV and φR).
Frequency fV > fR or fV Leading: Negative Pulses
Frequency fV < fR or fV Lagging: Positive Pulses
Frequency fV = fR and Phase Coincidence: High–Imped-
ance State
φR, φV
Phase Detector B Outputs (PDIP, SOG – Pins 4, 3)
These phase detector outputs can be combined externally
for a loop–error signal. A single–ended output is also avail-
able for this purpose (see PDout).
If frequency fV is greater than fR or if the phase of fV is
leading, then error information is provided by φV pulsing low.
φR remains essentially high.
If the frequency fV is less than fR or if the phase of fV is
lagging, then error information is provided by φR pulsing low.
φV remains essentially high.
If the frequency of fV = fR and both are in phase, then both
φV and φR remain high except for a small minimum time
period when both pulse low in phase.
LD
Lock Detector Output (PDIP – Pin 8, SOG – Pin 9)
Essentially a high level when loop is locked (fR, fV of same
phase and frequency). LD pulses low when loop is out of
lock.
SW1, SW2
Band Switch Outputs (PDIP – Pins 13, 14;
SOG – Pins 14, 15)
SW1 and SW2 provide latched open–drain outputs corre-
sponding to data bits numbers one and two. These outputs
can be tied through external resistors to voltages as high as
15 V, independent of the VDD supply voltage. These are
typically used for band switch functions. A logic 1 causes the
output to assume a high–impedance state, while a logic 0
causes the output to be low.
REFout
Buffered Reference Oscillator Output (PDIP, SOG –
Pin 15)
Buffered output of on–chip reference oscillator or exter-
nally provided reference–input signal.
POWER SUPPLY
VDD
Positive Power Supply (PDIP, SOG – Pin 5)
The positive power supply potential. This pin may range
from + 3 to + 9 V with respect to VSS.
VSS
Negative Power Supply (PDIP, SOG – Pin 7)
The most negative supply potential. This pin is usually
ground.
TYPICAL APPLICATIONS
UHF/VHF
TUNER OR
CATV
FRONT END
MC12073/74
PRESCALER
4.0 MHz
fin
MC145155–2
φR
φV
DATA CLK ENB
–
+ 1/2 MC1458*
KEYBOARD
CMOS
MPU/MCU
3 MC14489
LED DISPLAY
* The φR and φV outputs are fed to an external combiner/loop filter. See the Phase–Locked Loop — Low–Pass Filter Design page
for additional information. The φR and φV outputs swing rail–to–rail. Therefore, the user should be careful not to exceed the common
mode input range of the op amp used in the combiner/loop filter.
Figure 1. Microprocessor–Controlled TV/CATV Tuning System with Serial Interface
MOTOROLA
MC145151–2 through MC145158–2
11
11 Page | ||
| Páginas | Total 36 Páginas | |
| PDF Descargar | [ Datasheet MC145151-2.PDF ] | |
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