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A40MX04 Schematic ( PDF Datasheet ) - Actel Corporation

Teilenummer A40MX04
Beschreibung 40MX and 42MX FPGA Families
Hersteller Actel Corporation
Logo Actel Corporation Logo 




Gesamt 70 Seiten
A40MX04 Datasheet, Funktion
v5.0
40MX and 42MX FPGA Families
Features
High Capacity
• Single-Chip ASIC Alternative
• 3,000 to 54,000 System Gates
• Up to 2.5 kbits Configurable Dual-Port SRAM
• Fast Wide-Decode Circuitry
• Up to 202 User-Programmable I/O Pins
High Performance
• 5.6 ns Clock-to-Out
• 250 MHz Performance
• 5 ns Dual-Port SRAM Access
• 100 MHz FIFOs
• 7.5 ns 35-Bit Address Decode
HiRel Features
• Commercial, Industrial, and Military Temperature Plastic
Packages
Product Profile
Device
A40MX02
Capacity
System Gates
SRAM Bits
3,000
N/A
Logic Modules
Sequential
Combinatorial
Decode
Clock-to-Out
295
9.5 ns
SRAM Modules
(64x4 or 32x8)
N/A
Dedicated Flip-Flops
Maximum Flip-Flops
mClocks
oUser I/O (Maximum)
.cPCI
uBoundary Scan Test (BST)
t4Packages (by pin count)
ePLCC
ePQFP
hVQFP
sTQFP
taCQFP
PBGA
147
1
57
No
No
44, 68
100
80
w.daFebruary 2001
ww © 2001 Actel Corporation
A40MX04
6,000
N/A
547
9.5 ns
N/A
273
1
69
No
No
44, 68, 84
100
80
• Commercial, Military Temperature and MIL-STD-883
Ceramic Packages
• QML Certification
• Ceramic Devices Available to DSCC SMD
Ease of Integration
• Mixed Voltage Operation (5.0V or 3.3V I/O)
• Synthesis-Friendly Architecture to Support ASIC Design
Methodologies
• Up to 100% Resource Utilization and 100% Pin Fixing
• Deterministic, User-Controllable Timing
• Unique In-System Diagnostic and Verification Capability
with Silicon Explorer II
• Low Power Consumption
• IEEE Standard 1149.1 (JTAG) Boundary Scan Testing
• 5.0V and 3.3V Programmable PCI-Compliant I/O
A42MX09
14,000
N/A
348
336
N/A
5.6 ns
N/A
348
516
2
104
No
No
84
100, 160
100
176
A42MX16
24,000
N/A
624
608
N/A
6.1 ns
N/A
624
928
2
140
No
No
84
100, 160, 208
100
176
A42MX24
36,000
N/A
954
912
24
6.1 ns
N/A
954
1,410
2
176
Yes
Yes
84
160, 208
176
A42MX36
54,000
2,560
1,230
1,184
24
6.3 ns
10
1,230
1,822
6
202
Yes
Yes
208, 240
208, 256
272
1






A40MX04 Datasheet, Funktion
40MX and 42MX FPGA Families
The 42MX devices contain three types of logic modules:
combinatorial (C-modules), sequential (S-modules), and
decode (D-modules).
The C-module, shown in Figure 2, implements the following
function:
Y=!S1*!S0*D00+!S1*S0*D01+S1*!S0*D10+S1*S0*D11
where
S0=A0*B0
S1=A1+B1
The S-module, shown in Figure 3, is designed to implement
high-speed sequential functions within a single logic
module. The S-module implements the same combinatorial
logic function as the C-module while adding a sequential
element. The sequential element can be configured as
either a D flip-flop or a transparent latch. To increase
flexibility, the S-module register can be bypassed so that it
implements purely combinatorial logic.
A0
B0
A1
B1
S0
D00
D01
D10
D11
S1
Figure 2 C-Module Implementation
Y
D00
D01
YD
Q OUT
D10
D11 S0
S1
CLR
D00
D01
YD
Q OUT
D10
D11 S0 GATE
S1
Up to 7-Input Function Plus D-Type Flip-Flop with Clear
D0
D1
S
Y
DQ
GATE
CLR
OUT
Up to 7-Input Function Plus Latch
D00
D01 Y OUT
D10
D11 S0
S1
Up to 4-Input Function Plus Latch with Clear
Figure 3 S-Module Implementation
Up to 8-Input Function Same as C-Module)
6 v5.0

6 Page









A40MX04 pdf, datenblatt
Table 2 BST Instructions
Test Mode
Code Description
EXTEST
000
SAMPLE/
PRELOAD
001
JPROBE
011
USER
100
INSTRUCTION
HIGH Z
CLAMP
BYPASS
101
110
111
Allows the external circuitry and
board-level interconnections to
be tested by forcing a test
pattern at the output pins and
capturing test results at the
input pins.
Allows a snapshot of the signals
at the device pins to be
captured and examined during
device operation.
A private instruction allowing the
user to connect Actels Micro
Probe registers to the test
chain.
Allows the user to build
application-specific instructions
such as RAM READ and RAM
WRITE.
Refer to the IEEE Standard
1149.1 specification.
Refer to the IEEE Standard
1149.1 specification.
Enables the bypass register
between the TDI and TDO pins.
The test data passes through
the selected device to adjacent
devices in the test chain.
40MX and 42MX FPGA Families
12 v5.0

12 Page





SeitenGesamt 70 Seiten
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