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PDF MCP3551 Data sheet ( Hoja de datos )
| Número de pieza | MCP3551 | |
| Descripción | (MCP3551 / MCP3553) Low Power / Single-Channel 22-Bit Delta-Sigma ADCs | |
| Fabricantes | Micro Chip | |
| Logotipo |  |
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MCP3551/3
Low-Power, Single-Channel 22-Bit Delta-Sigma ADCs
Features
• 22-bit ADC in Small 8-pin MSOP Package with
Automatic Internal Offset and Gain Calibration
• Low-Output Noise of 2.5 µVRMS with Effective
Resolution of 21.9 bits (MCP3551)
• 3 µV Typical Offset Error
• 2 ppm Typical Full-Scale Error
• 6 ppm Maximum INL Error
• Total Unadjusted Error Less Than 10 ppm
• No Digital Filter Settling Time, Single-Command
Conversions through 3-wire SPI™ Interface
• Ultra-Low Conversion Current (MCP3551):
- 100 µA typical (VDD = 2.7V)
- 120 µA typical (VDD = 5.0V)
• Differential Input with VSS to VDD Common Mode
Range
• 2.7V to 5.5V Single-Supply Operation
• Extended Temperature Range:
- -40°C to +125°C
Applications
• Weigh Scales
• Direct Temperature Measurement
• 6-digit DVMs
• Instrumentation
• Data Acquisition
• Strain Gauge Measurement
Block Diagram
VREF
VSS VDD
VIN+
VIN-
3rd-Order
ΔΣ ADC
Modulator
w/ Internal
Calibration
Internal
Oscillator
VDD
POR
SCK
SDO
RDY
CS
Description
The Microchip Technology Inc. MCP3551/3 devices
are 2.7V to 5.5V low-power, 22-bit Delta-Sigma
Analog-to-Digital Converters (ADCs). The devices offer
output noise as low as 2.5 µVRMS, with a total
unadjusted error of 10 ppm. The family exhibits 6 ppm
Integral Non-Linearity (INL) error, 3 µV offset error and
less than 2 ppm full-scale error. The MCP3551/3
devices provide high accuracy and low noise
performance for applications where sensor
measurements (such as pressure, temperature and
humidity) are performed. With the internal oscillator
and high oversampling rate, minimal external
components are required for high-accuracy
applications.
This product line has fully differential analog inputs,
making it compatible with a wide variety of sensor,
industrial control or process control applications.
The MCP3551/3 devices operate from -40°C to +125°C
and are available in the space-saving 8-pin MSOP and
SOIC packages.
Package Types:
MCP3551/3
SOIC, MSOP
VREF 1
VIN+ 2
VIN– 3
VSS 4
8 VDD
7 CS
6 SDO/RDY
5 SCK
Device Selection Table
Part
Number
Sample
Rate
Effective
Resolution
MCP3551 13.75 sps
21.9 bits
MCP3553
60 sps
20.6 bits
50/60 Hz
Rejection
50/60 Hz
(simultaneous)
N/A
© 2005 Microchip Technology Inc.
DS21950B-page 1
1 page  
tRDY
tCSD
CS tCSL
SDO
/RDY
SCK
tDO
tSU
fSCK
tHI tLO
FIGURE 1-1:
Serial Timing.
VDD
CS
tPUCSL
FIGURE 1-2:
Power-up Timing.
MCP3551/3
tCSHSD
tDIS
© 2005 Microchip Technology Inc.
DS21950B-page 5
5 Page 
MCP3551/3
3.0 PIN DESCRIPTIONS
TABLE 3-1: PIN FUNCTION TABLES
Pin No.
Symbol
I/O/P
1
VREF
I
2
VIN+
I
3
VIN-
I
4
VSS
P
5
SCK
I
6
SDO/RDY
O
7 CS I
8
VDD
P
Type Identification: I = Input; O = Output; P = Power
Function
Reference Voltage Analog Input Pin
Non-inverting Analog Input Pin
Inverting Analog Input Pin
Ground Pin
Serial Clock Digital Input Pin
Data/Ready Digital Output Pin
Chip Select Digital Input Pin
Positive Supply Voltage Pin
3.1 Voltage Reference (VREF)
The MCP3551/3 devices accept single-ended refer-
ence voltages from 0.1V to VDD. Since the converter
output noise is dominated by thermal noise, which is
independent of the reference voltage, the output noise
is not significantly improved by diminishing the refer-
ence voltage at the VREF input pin. A reduced voltage
reference will significantly improve the INL perfor-
mance (see Figure 2-4); the INL max error is propor-
tional to VREF2.
3.2 Analog Inputs (VIN+, VIN-)
The MCP3551/3 devices accept a fully differential ana-
log input voltage to be connected on the VIN+ and VIN-
input pins. The differential voltage that is converted is
defined by VIN = VIN+ - VIN-. The differential voltage
range specified for ensured accuracy is from -VREF to
+VREF. However, the converter will still output valid and
usable codes with the inputs overranged by up to 12%
(see Section 5.0 “Serial Interface”) at room
temperature. This overrange is clearly specified by two
overload bits in the output code.
The absolute voltage range on these input pins extends
from VSS - 0.3V to VDD + 0.3V. Any voltage above or
below this range will create leakage currents through
the Electrostatic Discharge (ESD) diodes. This current
will increase exponentially, degrading the accuracy and
noise performance of the device. The common mode of
the analog inputs should be chosen such that both the
differential analog input range and the absolute voltage
range on each pin are within the specified operating
range defined in Section 1.0 “Electrical Characteris-
tics”.
3.3 Supply Voltage (VDD, VSS)
VDD is the power supply pin for the analog and digital
circuitry within the MCP3551/3. This pin requires an
appropriate bypass capacitor of 0.1 µF. The voltage on
this pin should be maintained in the 2.7V to 5.5V range
for specified operation. VSS is the ground pin and the
current return path for both analog and digital circuitry
of the MCP3551/3. If an analog ground plane is
available, it is recommended that this device be tied to
the analog ground plane of the Printed Circuit Board
(PCB).
3.4 Serial Clock (SCK)
SCK synchronizes data communication with the
device. The device operates in both SPI™ mode 1,1
and SPI mode 0,0. Data is shifted out of the device on
the falling edge of SCK. Data is latched in on the rising
edge of SCK. During CS high times, the SCK pin can
idle either high or low.
3.5 Data Output (SDO/RDY)
SDO/RDY is the output data pin for the device. Once a
conversion is complete, this pin will go active-low,
acting as a ready flag. Subsequent falling clock edges
will then place the 24-bit data word (two overflow bits
and 22 bits of data, see Section 5.0 “Serial Inter-
face”) on the SPI bus through the SDO pin. Data is
clocked out on the falling edge of SCK.
3.6 Chip Select (CS)
CS gates all communication to the device and can be
used to select multiple devices that share the same
SCK and SDO/RDY pins. This pin is also used to
control the internal conversions, which begin on the
falling edge of CS. Raising CS before the first internal
conversion is complete places the device in Single
Conversion mode. Leaving CS low will place the
device in Continuous Conversion mode (i.e., additional
internal conversions will automatically occur). CS may
be tied permanently low for two-wire Continuous
Conversion mode operation. SDO/RDY enters a
high-impedance state with CS high.
© 2005 Microchip Technology Inc.
DS21950B-page 11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet MCP3551.PDF ] | |
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