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PDF TXC-04228 Data sheet ( Hoja de datos )
| Número de pieza | TXC-04228 | |
| Descripción | E1Mx28 Device DS1 Mapper 28-Channel | |
| Fabricantes | Transwitch | |
| Logotipo |  |
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T1Mx28 Device
DS1 Mapper 28-Channel
TXC-04228
DATA SHEET
FEATURES
• Twenty-eight independent 1.544 Mbit/s DS1
mappers
• Single/dual byte-parallel Telecom Bus @ 6.48
MHz (28 slots) or 19.44 MHz (84 slots)
• Floating VT1.5 byte-synchronous mapping with
signaling only for use with or without a slip buffer
• Asynchronous mapping for DS1
• SONET mapping (VT1.5) or SDH mapping
(VC-4/AU-3/TU-11)
• AMI or B8ZS codec for DS1s, or NRZ
• Serial I/O for control of DS1 line interface
transceivers or framers
• Telecom Bus and DS1 loopbacks with integral
PRBS generator and analyzer
• VT1.5/TU-11 pointer tracking and generation
• VT1.5/TU-11 overhead processing and insertion
• One-second latched performance registers and
counters
• DS1 alarm detection and generation
• Internal ring port for use as a dual bus
14-channel mapper
• Gapped line clock option for Internet applications
without need for a framer
• Intel/Motorola-compatible microprocessor
interface
• 3-bit RDI support
• Boundary scan capability (IEEE 1149.1)
• Single +3.3 V, ±5 % power supply
• 456-lead plastic ball grid array
package (35 x 35 mm)
DESCRIPTION
The T1Mx28 is a 28-channel byte-synchronous and asyn-
chronous DS1 mapper. Four field-proven DS1MX7 DS1
Mapper chips are interconnected in a single compact pack-
age to permit higher application board densities. Both
SONET and SDH mappings are provided per Bellcore GR-
253-CORE (VT1.5) and ITU G.707 3-96. A single-dual add/
drop Telecom Bus is provided that can operate at either 6.48
or 19.44 MHz, which is compatible with other TranSwitch
devices. VT1.5/TU-11 pointer tracking and overhead extrac-
tion/processing with full error and alarm control is provided.
VT1.5/TU-11 pointer calculation and overhead assembly is
also provided. Alarm and error mappings from drop to add
and SONET/SDH to/from DS1 are provided. Jitter perfor-
mance is achieved with a fully digital threshold modulator
and DPLL that meets GR-253-CORE MTIE requirements
without external de-jitter buffers. For the DS1 line, AMI, B8ZS
and NRZ line codes are supported with full alarm detection
and generation per ANSI T1.231-1997. Each channel is
independently programmable for mixed service applications.
Access to status and control bits is provided via an Intel/
Motorola-compatible microprocessor interface. Diagnostic,
test, and maintenance functions are provided, including
boundary scan, PRBS generator/analyzer and loopbacks.
APPLICATIONS
• SONET/SDH terminal or add/drop multiplexers sup-
porting both asynchronous and byte-synchronous
modes
• Unidirectional or bidirectional ring applications
• SONET remote digital terminal equipment
• SONET CPE equipment requiring access to DS0s
• SONET/SDH test equipment
• Internet access equipment
SYSTEM SIDE
Line Transceiver Common
Control Interface
3 (x 4)
+3.3V
LINE SIDE
Add Bus
21
4 DS1 Dual Rail/
T1Mx28
NRZ Data &
u.comDrop Bus
Telecom Bus
Interface (x 2)
13
DS1 Mapper 28-Channel
TXC-04228
53
Clocks (x 28)
4
Line Transceiver
2 Alarm/Select Interface (x 28)
t4 Test Access Port Interface System
e for Boundary Scan
Clocks
heU.S. Patents No. 4,967,405; 5,033,064; 5,040,170;
s5,265,096; 5,289,507; 5,297,180; 5,528,598; 5,535,218
taU.S. and/or foreign patents issued or pending
Copyright 2001 TranSwitch Corporation
aT1Mx28 is a trademark of TranSwitch Corporation
.dTranSwitch and TXC are registered trademarks of TranSwitch Corporation
Microprocessor
Interface
Document Number:
PRELIMINARY TXC-04228-MB
Ed. 4, September 2001
w TranSwitch Corporation • 3 Enterprise Drive • Shelton, Connecticut 06484 • USA
ww Tel: 203-929-8810 • Fax: 203-926-9453 • www.transwitch.com
1 page  
Proprietary TranSwitch Corporation Information for use Solely by its Customers
DATA SHEET
T1Mx28
TXC-04228
• External lead-controlled shut down of all DS1 per A or B Telecom Bus line drive leads for
card protection
• Gapped clock option in place of signaling for 1536 kHz datacom in byte-synchronous
operation
• CRC-6 generation (DS1 input) and error counting (DS1 output) in byte-synchronous mapping
Mapping and Synchronizer Features
• Mapping to SONET or SDH columns according to GR-253-CORE or ITU G.709
• Per channel selectable asynchronous and byte-synchronous mapping to a floating
VT1.5 or TU-11 for both mapping and demapping
• Overhead assembly with BIP-2 calculation, REI-FEBE (microprocessor or received BIP-2
error), signal label (microprocessor value), RDI (microprocessor value or via received signal
label mismatch, VT AIS, VT LOP, or unequipped) and RFI (microprocessor value or DS1
Yellow from signaling highway)
• Pointer calculation (fixed at 78 for asynchronous, calculated for byte-synchronous mode) with
generated pointer increment and decrement counters (4 bits each)
• In byte-synchronous mode, line clock may be an input (’modified byte-synchronous mode’) or
an output (’true byte-synchronous mode’)
• Multiplexing of signaling bits from the signaling highway with P0/P1 bit generation
• Unequipped and unassigned VT payload generation
• VT AIS generation (microprocessor value, AIS from signaling highway, loss of frame on byte-
synchronous, or AIS/LOS/external lead from line decoder)
• Threshold modulator to reduce demapping jitter and wander
• Tracking of input multiframe pulses by pointer movements in byte-synchronous mode
Demapping and Desynchronizer Features
• Asynchronous or byte-synchronous per channel, programmable to match mapper mode
• Digital PLL with 2 Hz low pass filter to track up to ± 250 Hz nominal DS1 signal providing a
smooth clock output with no need for an external de-jitter buffer
• Separate ± 5 byte pointer leak buffer with programmable dual slope leak rate
(8 ms to 2048 ms per bit in 8 ms steps, automatically doubled to 16 ms to 4096 ms per bit in
16 ms steps within ± 12 bits of center of pointer leak buffer); meets Bellcore MTIE with
minimal software support
• Power down with all-zeros or all-ones sent to line interface
• Demapping of SONET or SDH columns according to GR-253-CORE or ITU G.709
• Asynchronous and byte-synchronous demapping of a floating VT1.5/TU-11
• Pointer tracking and extraction of overhead (V5 and Z7/K4), LOP, AIS, SS and NDF with
received pointer increment and decrement counters (4 bits each)
• Overhead processing with BIP-2 calculation and error counting (12-bit, with overflow), REI
(FEBE) counting (12-bit, with overflow), RDI (1- and 3-bit)/RFI signal label debouncing and
detection, signal label mismatch/unequipped detection
• Demultiplexing of signaling bits to the signaling highway with multiframe generation for byte-
synchronous
• DS1 AIS from microprocessor value, VT AIS, VT LOP, signal label mismatch or unequipped
• DS1 RAI (Yellow) to signaling highway from RFI
- 5 of 150 -
PRELIMINARY TXC-04228-MB
Ed. 4, September 2001
5 Page 
Proprietary TranSwitch Corporation Information for use Solely by its Customers
DATA SHEET
T1Mx28
TXC-04228
Byte-synchronous mapping supports the independent transmission of signaling through defined nibbles in the
VT1.5/TU-11 structure, as shown in Figure 2. The T1Mx28 provides Receive and Transmit Signaling Stores to
synchronize signaling and framing bits to and from a DS1 Framer or switching stage with the Mapper and
Demapper blocks. Signaling is received through the RNEGn/RSIGLn leads in byte-synchronous mode, being
clocked in with LRCLKn. Signaling is sent out on the TNEGn/TSIGLn leads in byte-synchronous mode, using
LTCLKn. TranSwitch framers like the T1Fx8 (TXC-03108) can utilize the signaling bits on the signaling high-
ways for automatic signaling propagation between SONET/SDH byte-synchronous mapping and DS1 lines.
For applications using the full DS1 payload in byte-synchronous mode, the RNEGn/RSIGLn leads can be pro-
grammed to supply gapped clock (RGCOn), as can the TNEGn/TSIGLn leads (TGCOn).
The Receive and Transmit Alarm Control blocks work in conjunction with the Decoder/Coder and Input/Output
Timing blocks as well as the Receive and Transmit Signaling Store blocks to move DS1 alarm signals in and
out of the T1Mx28. The Receive Alarm Control block detects specific bits from the receive signaling highway,
such as AIS or RAI (Yellow), for forwarding to the Synchronizer/Mapper block as AIS and RFI. It also gathers
LOS and AIS from the Receive Line Interface. The LAISn input lead may be used for forwarding an externally
detected Loss of Signal or Loss of Clock, or as a general interrupt input. The Transmit Alarm Control block
translates RFI and AIS from the Desynchronizer/Demapper block along with microprocessor controls to set
specific bits on the transmit signaling highway. TranSwitch framers like the T1Fx8 (TXC-03108) can utilize the
control bits on the signaling highways for automatic alarm propagation between SONET/SDH and DS1 lines.
For card protection schemes, control input leads ACSO(BCSO), when driven low, cause all of the output leads
for the fourteen Line Interfaces associated with the A or B Telecom Bus to go low.
The Synchronizer/Mapper block takes the clock and data from the Receive Line Interface in asynchronous
mode, threshold modulates it with SRCLK, buffers it in a FIFO, inserts the data bits in the information bit posi-
tions of the asynchronous VT1.5/TU-11, and stuffs it using the two stuff opportunity bits with indication in the
C1 and C2 bits, as shown in Figure 2. The stuffing matches the received DS1 clock to the bit positions avail-
able based on the SONET/SDH network clock supplied to the T1Mx28 in the Add Telecom Bus Clocks, AACLK
and BACLK, and the AAC1J1V1 and BAC1J1V1 signals. Optional overhead bytes J2, Z6/N2, O and part of Z7
are taken from microprocessor-written values.
The Synchronizer/Mapper block takes the clock, frame and data from the Receive Line Interface in byte-
synchronous mode, buffers it in a FIFO and writes it to defined byte positions in the byte-synchronous VT1.5/
TU-11 along with the optional overhead bytes J2, Z6/N2 and part of Z7, which are taken from microprocessor-
written values. For byte-synchronous mode the signaling bits are taken from the Receive Signaling Store and
mapped to the correct positions in the VT1.5/TU-11. The 500-microsecond long VT superframe shown in
Figure 2 is repeated six times, being synchronized to the RSYNCn 3.0 millisecond input. The P1P0 bits are
generated to indicate which signaling or framing bits are being carried in a specific VT superframe and are
related to RSYNCn. FIFO conditions are monitored and can lead to increment or decrement requests of the VT
Termination block. Synchronization changes in RSYNCn are monitored for possible NDF requests.
The VT Termination block takes the mapped data and optional overhead together with any frame, increment or
decrement indications associated with byte-synchronous mode from the Synchronizer/Mapper block. The V5
and Z7 bytes are built from one of several received DS1 alarm sources (the received alarms, Ring Port error
conditions, or microprocessor-written values). Parity is then calculated over the payload. V1 and V2 are set to
78, positioning V5 just after V1 for asynchronous mode only. For byte-synchronous mode (true byte-synchro-
nous or modified byte-synchronous), the V1 and V2 bytes are generated to track the phase of the incoming
DS1 signals relative to AACLK and BACLK; two four-bit counters are provided to keep track of pointer incre-
ments and pointer decrements generated. If a new position for the RSYNCn pulse is generated, this block will
generate an NDF along with the new pointer. If the T1Mx28 acts as a clock source, the ALO or BLO lead will be
used to provide this clock and it must be frequency locked to the STS-1 or STM-1 clock, or pointer justifications
and/or mapping errors will result. If AIS is to be generated the entire payload is ones. If unassigned (Idle) is to
be generated, an all-zeros payload with a valid V5 is generated. If an unequipped is to be generated, an all-
zeros payload including V5 is generated.
- 11 of 150 -
PRELIMINARY TXC-04228-MB
Ed. 4, September 2001
11 Page | ||
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| PDF Descargar | [ Datasheet TXC-04228.PDF ] | |
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