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PDF TXC-04222 Data sheet ( Hoja de datos )
| Número de pieza | TXC-04222 | |
| Descripción | 28-Channel Dual Bus High Density Mapper | |
| Fabricantes | Transwitch | |
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TEMx28 Device
28 Channel Dual Bus High Density Mapper
TXC-04222
DATA SHEET
FEATURES
• Add/drop up to 28 E1, DS1, or VT/TU payloads
from two add and two drop STM-1/VC4, STS-3
buses
• Add bus and drop bus timing modes
• Cross mapping applications (DS1 mapped to/from
VT2/TU-12s)
• Selectable HDB3/B8ZS/AMI positive/negative rail,
NRZ, or VT/TU interfaces per channel
• H4 multiframe option in place of Telecom Bus V1
pulse
• Digital desynchronizer
• Drop buses are monitored for parity, loss of clock,
and upstream AIS
• Performance counters for pointer movements,
BIP-2 errors, REI and coding violations
• Single-bit or three-bit RDI operation per channel
• Tandem connection capability per ETSI standards
• J2 trail trace comparison option
• Processor access to H1/H2, H4 overhead bytes,
and V1/V2 and V4 bytes
• Selectable positive, negative or positive/negative
alarm transition interrupt options
• Line and facility loopbacks, generation of BIP-2
and REI errors, PRBS generator and analyzer per
channel
• Polling registers and global summary alarm status
• One second measurements: counters and alarms
• Software device driver is provided
• IEEE 1149.1 standard boundary scan
• +3.3 V and 1.8 V power supplies,
5 V tolerant I/O leads
• 376-lead plastic ball grid array (PBGA) package
(23 mm x 23 mm)
DESCRIPTION
The TEMx28 device is designed for add/drop
multiplexer, terminal multiplexer, and dual and single
unidirectional ring applications. Up to 28 E1, DS1, or
VT/TU payloads are mapped to and from VT1.5/TU-11s
and VT2/TU-12s carried in an STM-1 VC-4 or STS-3
format. The device interfaces to a multiple-segment,
byte-parallel SDH/SONET-formatted bus at the 19.44
Mbyte/s byte rate. The E1 and DS1 signals can be
HDB3 or B8ZS/AMI rail signals, or NRZ signals. The
VT/TU interface can be provided with or without the
overhead bytes for virtual concatenation applications.
The TEMx28 performs pointer tracking and overhead
byte processing, including single-bit or three-bit RDI
operation, and optional tandem connection capability. All
overhead bytes, including the V1/V2/V4 bytes, are
provided for microprocessor access.
The TEMx28 can generate receive and transmit line
AIS, transmit unequipped and supervisory unequipped
channels, and transmit VT/TU AIS, in addition to
standards-compliant overhead byte monitoring. It also
provides test features and a microprocessor interface.
APPLICATIONS
• 3 STS-3/STM-1 to 1.544 Mbit/s and 2.048 Mbit/s
add/drop mux/demux
• Unidirectional or bidirectional ring applications
• STS-3/STM-1 termination terminal mode multiplexer
• STS-3/STM-1 test equipment
STM-1/STS-3
SDH/SONET SIDE
+3.3 V
+1.8 V
Desynchronizer Clock
LINE SIDE
A - side
drop bus
TEMx28
Channel 1
A - side
add bus
mB - side
odrop bus
.cB - side
uadd bus
28 Channel Dual Bus
High Density Mapper
TXC-04222
E1 or DS1 lines
(up to)
Channel 28
et4 Boundary
e Scan
Microprocessor Controls
interface
shU.S. and/or foreign patents issued or pending
taCopyright 2003 TranSwitch Corporation
aPHAST, TEMx28, TranSwitch and TXC
are registered trademarks of TranSwitch Corporation
.d TranSwitch Corporation • 3 Enterprise Drive • Shelton, Connecticut 06484
www Tel: 203-929-8810 • Fax: 203-926-9453 • www.transwitch.com
Document Number:
TXC-04222-MB, Ed. 6
June 2003
• USA
1 page  
Proprietary TranSwitch Corporation Information for use Solely by its Customers
DATA SHEET
TEMx28
TXC-04222
FEATURES
The following is a detailed list of features supported by the TEMx28:
• Bus Modes of operation (Each Channel)
• Drop Mode Only
• Drop from A or B
• Add Mode only
• Add to A or B
• Add to A and B
• Single Unidirectional Ring
• Drop from A, Add to A
• Drop from B, Add to B
• Multiplexer
• Drop from A, Add to B
• Drop from B, Add to A
• Dual Protection Ring
• Drop from A, Add to A and B
• Drop from B, Add to B and A
• Bus Timing
• Drop Bus Timing
• Add Bus Timing Derived from the same named Drop Bus
• Add Bus Timing
• Add Bus Timing is independent of the Drop Bus
• Lead Selectable
• SONET/SDH COMBUS Interface
• Drop Bus Timing Enabled
• Drop Bus: C1J1V1, SPE, Byte Wide Data, Clock, Parity
• Add Bus: Byte Wide Data, Parity, Add Indicator
• Option: Clock, C1J1V1, and SPE are Outputs
• Add Bus Timing Enabled
• Drop Bus: C1J1V1, SPE, Byte Wide Data, Clock, Parity
• Add Bus: Clock, C1J1V1, SPE are inputs; Byte Wide Data, Parity, Add Indicator are Outputs.
• Mappings
• Maximum of up to 28 Channels
• DS1/E1 Line Asynchronous Formats, or VC-11/VC-12s
• Independent VT1.5/TU-11 or VT2/TU12 Selection per Channel for both Drop and Add Buses
• Cross Mapping: DS1 mapped into VT1.5/TU-12
• SONET/SDH Operating Formats
• STS-3 STS-1 (19.44 Mbyte/s)
• STM-1 VC-4/TUG-3/TUG-2 (19.44 Mbyte/s)
• STM-1 AU-3s (19.44 Mbyte/s)
- 5 of 246 -
TXC-04222-MB, Ed. 6
June 2003
5 Page 
Proprietary TranSwitch Corporation Information for use Solely by its Customers
DATA SHEET
TEMx28
TXC-04222
Each drop bus (A and B) is monitored for parity errors, loss of clock, H4 multiframe alignment if selected, and
an upstream SDH/SONET AIS indication. The TEMx28 can monitor either the TOH E1 order wire bytes or the
H1/H2 bytes for an upstream AIS indication.
Each TU/VT Terminate block (A and B side) performs pointer processing using the V1 and V2 bytes. The
pointer bytes are monitored for loss of pointer, Alarm Indication Signal (AIS), and a New Data Flag (NDF). The
pointer tracking process is based on ETSI/ITU-T standards, which also meets ANSI requirements. Pointer
increments and decrements are also counted, and the size bits are monitored for the correct value. This block
also processes and monitors the various alarms found in the four overhead bytes. These operations including
signal label mismatch detection, unequipped status detection, BIP-2 parity error detection and error counter,
REI error counting, and single-bit or three-bit Remote Defect Indications (RDI). The TEMx28 performs a
16-byte J2 trail trace comparison on the channels selected. For 64-byte messages, the bytes are stored in a
memory map segment for a microprocessor read cycle. The device also provides the TU tandem connection
feature and performs the 16-byte message comparison for the N2 (formerly known as Z6) byte message.
All VT/TU overhead bytes, eight overhead communications channel bits (O-bits), the V1/V2 pointer bytes, and
the V4 byte for each channel are available for a microprocessor read cycle. Also, the E1 order wire bytes, the
H1/H2 pointer bytes, and the H4 bytes from the upstream circuitry are also available for a microprocessor read
cycle.
A control bit for each port selects the TU/VT from either the A Drop or B Drop bus. The TU/VT is destuffed in the
Destuff block using majority logic rules for the three sets of three justification control bits to determine if the two
S-bits are data bits or frequency justification bits.
The Desynchronizer block removes the effects on the DS1 or E1 output of systemic jitter that might occur
because of signal mappings and pointer movements in the network. The Desynchronizer block is comprised of
a pointer leak buffer and a loop buffer. The pointer leak buffer spaces bursts of pointer movements more
gradually over time and can accept up to five consecutive pointer movements. The loop buffer consists of a
digital loop filter, which is designed to track the frequency of the received signal and to remove both
transmission and stuffing jitter.
The Channel n Receive Interface block of each channel provides either NRZ data, positive and negative rail
signal, or a VT/TU interface. Receive data (towards the line), for each of the channels, can be clocked out on
either rising or falling edges of the clock. In addition, a control bit is provided for forcing the data and clock
signals to a high impedance state (tristate), or to the zero state.
In the add (transmit) direction, the TEMx28 accepts a clock and either NRZ data or positive and negative rail
signals. Data, for each of the channels, can be clocked in on either the falling or rising edge of the clock. In the
NRZ mode, an external loss of clock indication or external coding violations can be provided. For the rail signal,
coding violations are counted, and there is a loss of signal detector. A DS1/E1 AIS detector is also provided.
Each channel can also be configured for VT/TU interface for Virtual Concatenation data applications. When this
interface is selected, a clock signal is provided for strobing in data for either the A or B bus. Four framing pulses
are also provided which define the starting location of the VT1.5/TU-11 and VT2/TU-12. An option is provided
for including the four overhead bytes. However, except for bits 1 and 2 in the K4 bytes, the other bits are
ignored. Bits 1 and 2 in the K4 byte carry an extended signal label and information pertaining to the payload
position within the Virtual Concatenation channel. The Virtual Concatenation channel will be assigned to n
VT/TUs based on the data bandwidth required for the application.
- 11 of 246 -
TXC-04222-MB, Ed. 6
June 2003
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet TXC-04222.PDF ] | |
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