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ST95020 Schematic ( PDF Datasheet ) - ST Microelectronics

Teilenummer ST95020
Beschreibung (ST950x0) 4K/2K/1K Serial SPI EEPROM with Positive Clock Strobe
Hersteller ST Microelectronics
Logo ST Microelectronics Logo 




Gesamt 18 Seiten
ST95020 Datasheet, Funktion
ST95040
ST95020, ST95010
4K/2K/1K Serial SPI EEPROM with Positive Clock Strobe
1 MILLION ERASE/WRITE CYCLES
40 YEARS DATA RETENTION
SINGLE SUPPLY VOLTAGE
– 4.5V to 5.5V for ST950x0
– 2.5V to 5.5V for ST950x0W
SPI BUS COMPATIBLE SERIAL INTERFACE
2 MHz CLOCK RATE MAX
BLOCK WRITE PROTECTION
STATUS REGISTER
16 BYTE PAGE MODE
WRITE PROTECT
SELF-TIMED PROGRAMMING CYCLE
E.S.D.PROTECTION GREATER than 4000V
SUPPORTS POSITIVE CLOCK SPI MODES
8
1
PSDIP8 (B)
0.25mm Frame
8
1
SO8 (M)
150mil Width
Figure 1. Logic Diagram
DESCRIPTION
The ST950x0 is a family of Electrically Erasable
Programmable Memories (EEPROM) fabricated
with STMicroelectronics’s High Endurance Single
Polysilicon CMOS technology. Each memory is
accessed by a simple SPI bus compatible serial
interface. The bus signals are a serial clock input
(C), a serial data input (D) and a serial data output
(Q).
Table 1. Signal Names
C Serial Clock
D Serial Data Input
Q Serial Data Output
S Chip Select
W Write Protect
HOLD
Hold
VCC Supply Voltage
VSS Ground
VCC
D
C
S
W
HOLD
ST950x0
Q
VSS
AI01435B
June 1998
1/18






ST95020 Datasheet, Funktion
ST95040, ST95020, ST95010
Figure 6. Read Operation Sequence
S
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
C
INSTRUCTION
BYTE ADDRESS
D A8 A7 A6 A5 A4 A3 A2 A1 A0
HIGH IMPEDANCE
Q
DATA OUT
76543210
AI01440
Notes: A8 = A7 = 0 on ST95010; A8 = 0 on ST95020; A8 is only active on ST95040.
Table 4. Write Protected Block Size
Status Register Bits
BP1 BP0
Protected Block
0 0 none
0 1 Upper quarter
1 0 Upper half
1 1 Whole memory
Array Address Protected
ST95040
ST95020
ST95010
none
none
none
180h - 1FFh
C0h - FFh
60h - 7Fh
100h - 1FFh
80h - FFh
40h - 7Fh
000h - 1FFh
00h - FFh
00h - 7Fh
Write Status Register (WRSR)
The WRSR instruction allows the user to select the
size of protected memory. The user may read the
blocks but will be unable to write within the pro-
tected blocks. The blocks and respective WRSR
control bits are shown in Table 4.
When the WRSR instruction and the 8 bits of the
Status Register are latched-in, the internal write
cycle is then triggered by the rising edge of S.
This rising edge of S must appear no later than the
16th clock cycle of the WRSR instruction of the
Status Register content (it must not appear a 17th
clock pulse before the rising edge of S), otherwise
the internal write sequence is not performed.
Read Operation
The chip is firstselected by putting S low. The serial
one byte read instruction is followed by a one byte
address (A7-A0), each bit being latched-in during
the rising edge of the clock (C). Bit 3 (see Table 3)
of the read instruction contains address bit A8
(most significant address bit). Then the data stored
in the memory at the selected addressis shifted out
on the Q output pin; each bit being shifted out
during the falling edge of the clock (C). The data
stored in the memory at the next address can be
read in sequence by continuing to provide clock
pulses. The byte address is automatically incre-
mented to the next higher address after each byte
of data is shifted out. When the highest address is
reached, the address counter rolls over to 0h allow-
ing the read cycle to be continued indefinitely. The
read operation is terminated by deselecting the
chip. The chip can be deselectedat anytime during
data output. Any read attempt during a write cycle
will be rejected and will deselect the chip.
6/18

6 Page









ST95020 pdf, datenblatt
ST95040, ST95020, ST95010
Table 8. AC Characteristics
ST95040 / 020 / 010
Symbol Alt
Parameter
VCC = 4.5V to 5.5V,
TA = 0 to 70°C,
TA = –40 to 85°C
VCC = 4.5V to 5.5V,
TA = –40 to 125°C
VCC = 2.5V to 5.5V,
TA = 0 to 70°C,
TA = –40 to 85°C
Min Max Min Max Min Max
Unit
fC fC Clock Frequency
D.C. 2 D.C. 2 D.C. 1 MHz
tSLCH
tCSS S Active Setup Time
100
100
200 ns
tCHSL
S Not Active Hold
Time
100
100
200 ns
tCH (1)
tCLH Clock High Time
190
200
400 ns
tCL(1)
tCLL Clock Low Time
200
200
400 ns
tCLCH
tRC Clock Rise Time
1 1 1 µs
tCHCL
tFC Clock Fall Time
1 1 1 µs
tDVCH
tDSU Data In Setup Time
50
50 100 ns
tCHDX
tDH Data In Hold Time
50
50 100 ns
tDLDH
tRI Data In Rise Time
1 1 1 µs
tDHDL
tFI Data In Fall Time
1 1 1 µs
tHHCH
tHSU HOLD Setup Time
100
100
200 ns
tHLCH
Clock Low Hold Time
90
90 200 ns
tCLHL
tHH HOLD Hold Time
80
80 200 ns
tCLHH
Clock Low Set-up
Time
100
100
200 ns
tCHSH
S Active Hold Time
200
200
200 ns
tSHCH
S Not Active Setup
Time
100
100
200 ns
tSHSL
tCSH S Deselect Time
200
200
200 ns
tSHQZ
tDIS Output Disable Time
150
150
200 ns
tCLQV
tV
Clock Low to Output
Valid
240
300
400 ns
tCLQX
tQLQH (2)
tQHQL (2)
tHO Output Hold Time
tRO Output Rise Time
tFO Output Fall Time
0 0 0 ns
100 100 200 ns
100 100 200 ns
tHHQX
tL Z
HOLD High to Output
Low-Z
100
100
200 ns
tHLQZ
tHZ
HOLD Low to Output
High-Z
130
130
200 ns
tW tWP Write Cycle Time
10
Notes: 1. tCH + tCL 1/fc
2. Value guaranteed by characterization, not 100% tested in production.
10
10 ms
12/18

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