PDF ST95022 Data sheet ( Hoja de datos )

Número de pieza	ST95022
Descripción	2 Kbit Serial SPI EEPROM with High Speed Clock
Fabricantes	ST Microelectronics
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No Preview Available ! ST95022 2 Kbit Serial SPI EEPROM with High Speed Clock HIGH SPEED CLOCK RATE: – 2.1 MHz Max 1,000,000 ERASE/WRITE CYCLES 40 YEARS DATA RETENTION SINGLE 4.5V to 5.5V SUPPLY VOLTAGE SPI BUS COMPATIBLE SERIAL INTERFACE BLOCK WRITE PROTECTION STATUS REGISTER 16 BYTE PAGE MODE WRITE PROTECT SELF-TIMED PROGRAMMING CYCLE E.S.D.PROTECTION GREATER than 4000V SUPPORTS POSITIVE CLOCK SPI MODES 8 1 SO8 (M) 150mil Width DESCRIPTION The ST95022 is an high speed 2 Kbit Electrically Erasable Programmable Memory (EEPROM) fab- ricated with STMicroelectronics’s High Endurance Single Polysilicon CMOS technology. The memory is accessed by a simple SPI bus compatible serial interface. The bus signals are a serial clock input (C), a serial data input (D) and a serial data output (Q). Table 1. Signal Names C Serial Clock D Serial Data Input Q Serial Data Output S Chip Select W Write Protect HOLD Hold VCC Supply Voltage VSS Ground Figure 1. Logic Diagram VCC D C S W HOLD ST95022 VSS Q AI01722 February 1999 1/16 1 page Figure 5. Block Diagram HOLD W S C D Q Control Logic High Voltage Generator I/O Shift Register Address Register and Counter Data Register Status ST95022 Block Protect 16 Bytes X Decoder AI01272 tected blocks. The blocks and respective WRSR control bits are shown in Table 4. When the WRSR instruction and the 8 bits of the Status Register are latched-in, the internal write cycle is then triggered by the rising edge of S. This rising edge of S must appear no later than the 16th clock cycle of the WRSR instruction of the Status Register content (it must not appear a 17th clock pulse before the rising edge of S), otherwise the internal write sequence is not performed. Table 4. Write Protected Block Size Status Register Bits BP1 BP0 Array Addresses Protected Protected Block 00 none none 0 1 C0h - FFh Upper quarter 1 0 80h - FFh Upper half 1 1 00h - FFh Whole memory 5/16 5 Page Table 8. AC Characteristics (TA = –40 to 125°C; VCC = 4.5V to 5.5V) Symbol Alt Parameter Test Condition fC fC Clock Frequency tSLCH tCSS S Active Setup Time (relative to the rising edge of C) tCHSL tCH (1) tCL(1) S Not Active Hold Time (relative to the rising edge of C) tCLH Clock High Time tCLL Clock Low Time tCLCH tRC Clock Rise Time tCHCL tFC Clock Fall Time tDVCH tDSU Data In Setup Time tCHDX tDH Data In Hold Time tDLDH tRI Data In Rise Time tDHDL tFI Data In Fall Time tHHCH tHSU HOLD Setup Time tHLCH Clock Low Hold Time after HOLD Active tCLHL tCLHH tHH HOLD Hold Time Clock Low Set-up Time before HOLD Inactive tCHSH S Active Hold Time (relative to the rising edge of C) tSHCH S Not Active Setup Time (relative to the rising edge of C) tSHSL tSHQZ tCSH S Deselect Time tDIS Output Disable Time tCLQV tV Clock Low to Output Valid tCLQX tHO Output Hold Time tQLQH (2) tRO Output Rise Time tQHQL (2) tFO Output Fall Time tHHQX tLZ HOLD High to Output Low-Z tHLQZ tHZ HOLD Low to Output High-Z tW tWP Write Cycle Time Notes: 1. tCH + tCL ≥ 1/fc 2. Value guaranteed by characterization, not 100% tested in production. ST95022 Min D.C. 100 Max 2.1 Unit MHz ns 100 190 190 1 1 50 50 1 1 100 100 80 100 ns ns ns µs µs ns ns µs µs ns ns ns ns 200 ns 100 200 150 240 0 100 100 100 200 7 ns ns ns ns ns ns ns ns ns ms 11/16 11 Page

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