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PDF UDA1328T Data sheet ( Hoja de datos )
| Número de pieza | UDA1328T | |
| Descripción | Multi-channel filter DAC | |
| Fabricantes | NXP Semiconductors | |
| Logotipo |  |
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INTEGRATED CIRCUITS
DATA SHEET
UDA1328T
Multi-channel filter DAC
Product specification
Supersedes data of 2000 Jan 04
File under Integrated Circuits, IC01
2001 Mar 27
1 page  
Philips Semiconductors
Multi-channel filter DAC
6 BLOCK DIAGRAM
Product specification
UDA1328T
handbook, full pagewidth
BCK
WS
DATAI12
DATAI34
DATAI56
10
11
12
13
14
TEST1
SYSCLK
27
16
VOUT1P
VOUT1N
28
29
VOUT3
1
VOUT5
4
VDDD
21
UDA1328T
DIGITAL
INTERFACE
VSSD
20
CONTROL
INTERFACE
VOLUME/MUTE/DE-EMPHASIS
9
STATIC
23
MUTE
24
DEEM1
25
DEEM0
18
L3CLOCK
19
L3DATA
17
L3MODE
26
DS
INTERPOLATION FILTER
6-CHANNEL NOISE SHAPER
DAC
DAC
DAC
DAC
8
TEST3
22
TEST2
32
VOUT2P
31
VOUT2N
2
VOUT4
DAC
DAC
5
VOUT6
6
VDDA
7, 15
n.c.
3
VSSA
30
Vref
MGR979
2001 Mar 27
Fig.1 Block diagram.
5
5 Page 
Philips Semiconductors
Multi-channel filter DAC
Product specification
UDA1328T
9 L3 INTERFACE DESCRIPTION
The following system and digital sound processing
features can be controlled in the microcontroller mode of
the UDA1328:
• Data input format
• De-emphasis for 32, 44.1, 48 and 96 kHz
• Volume control: master and for individual channels
• Soft or quick mute: master and for individual channels
• Output polarity control: master and for individual
channels
• Digital silence control: master and for individual
channels
• Power-down mode.
The exchange of data and control information between the
microcontroller and the UDA1328 is accomplished via a
serial hardware interface comprising the following pins:
L3DATA: microcontroller interface data line
L3MODE: microcontroller interface mode line
L3CLOCK: microcontroller interface clock line.
Information transfer via the microcontroller bus is
organized LSB first and is in accordance with the so called
‘L3’ format, in which two different modes of operation can
be distinguished. The address mode and data transfer
mode are illustrated in Figs 6 and 7.
The address mode is required to select a device
communicating via the L3-bus and to define the
destination registers for the data transfer mode. Data
transfer for the UDA1328 can only be in one direction;
input to the UDA1328 to program its sound processing and
other functional features.
9.1 Address mode
The address mode is used to select a device for
subsequent data transfer and to define the destination
registers. The address mode is characterized by L3MODE
being LOW and a burst of 8 pulses on L3CLOCK,
accompanied by 8 data bits. The fundamental timing is
shown in Fig.6. Data bits 0 and 1 indicate the type of
subsequent data transfer as given in Table 5.
Table 5 Selection of data transfer
BIT 1
0
0
1
1
BIT 0
TRANSFER
0 data (volume, de-emphasis, mute,
digital silence mode, polarity control)
1 not used
0 status (system clock frequency,
data input format, mute mode,
power control)
1 not used
Data bits 7 to 2 represent a 6-bit device address, with bit 7
being the MSB and bit 2 the LSB. The address of the
UDA1328 is 000100 (bit 7 to bit 2) when L3ADR
(DEEM0) = LOW or 000101 when L3ADR = HIGH. In the
event that the UDA1328 receives a different address, it will
deselect its microcontroller interface logic.
9.2 Data transfer mode
The selection preformed in the address mode remains
active during subsequent data transfers, until the
UDA1328 receives a new address command. The
fundamental timing of data transfers is essentially the
same as in the address mode, shown in Fig.6. The
maximum input clock and data rate is 64fs. All transfers are
byte wise, i.e. they are based on groups of 8 bits. Data will
be stored in the UDA1328 after the eighth bit of a byte has
been received. A multibyte transfer is illustrated in Fig.8.
9.2.1
PROGRAMMING THE SOUND PROCESSING AND
OTHER FEATURES
The sound processing and other feature values are stored
in independent registers. The first selection of the registers
is achieved by the choice of data type that is transferred.
This is performed in the address mode, bit 1 and bit 0
(see Table 5). The second selection is performed by the
2 MSBs of the data byte (bit 7 and bit 6). The other bits in
the data byte (bit 5 to bit 0) is the value that is placed in the
selected registers.
When the data transfer of type ‘data’ is selected, the
features volume, sub volume, de-emphasis, mute, digital
silence settings, output polarity control and channel
selection can be controlled. When the data transfer of type
‘status’ is selected, the features system clock frequency,
data input format, mute mode and power control can be
controlled.
2001 Mar 27
11
11 Page | ||
| Páginas | Total 28 Páginas | |
| PDF Descargar | [ Datasheet UDA1328T.PDF ] | |
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