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MV20556 Schematic ( PDF Datasheet ) - Mosel Vitelic

Teilenummer MV20556
Beschreibung 8 - Bit MCU Mouse Controller
Hersteller Mosel Vitelic
Logo Mosel Vitelic Logo 




Gesamt 30 Seiten
MV20556 Datasheet, Funktion
MOSEL VITELIC INC.
July 1997
Preliminary
Features
General 8051 instruction family compatible
Operate at voltage 5.0V.
No External Memory is supported
8 bit bus I/O ports
4 K byte ROM
128 byte RAM
128 byte depth stack
Two 16 bit Timers (Event Counters)
15 programmable I/O pins
Five interrupt sources
Programmable serial UART channel
Direct LED drive output
MV20556
8 - Bit MCU Mouse Controller
Bit operation instructions
Page free jumps
8 - bit Unsigned Division
8 - bit Unsigned Multiply
BCD arithmatic
Direct Addressing
Indirect Addressing
Nested Interrupt
Two priority level interrupt
A full duplex serial I/O port
Working at 16/25/40 MHz Clock
Full static operation: 3 MHz through 16 MHz
Description
The MVI MV20556 is an 8 - bit single chip
microcontroller. It provides hardware features and
powerful instruction set that are necessary to make it a
versatile and cost effective controller for mouse
applications which needs up to 4K byte internal
memory either for program or for data and mixed.
A serial input / output port is provided for I/O
expansion, Inter - processor communications, full
duplex UART.
Ordering Information
MV20556ajk - pqrs
a: process identifier. { C:=COMS }
jk: working clock in MHz. { 16 }
pqr: production code { 001, ..., 999 }
s: package type. { P: 20L 300 mil PDIP }
Postfix
blank
N
S
Package
dice
20L PDIP
20L SOP
Pin/Pad
Configuration
page 25
page 1
page 1
Dimension
page 25
page 23
page 24
Logo Size at
Top Marking
-
4.5 x 3.8 mm
4.0 x 3.4 mm
Pin Configuration
RES 1
RXD/P 3.0 2
TXD/P 3.1 3
XTA2 4
XTAL1 5
#INT0/P 3.2 6
#INT1/P 3.3 7
T0/P 3.4 8
T1/P 3.5 9
VSS 10
MV20556
20L PDIP
300 mil
(Top View)
20L SOP
(Top View)
20 VDD
19 P 1.7
18 P 1.6
17 P 1.5
16 P 1.4
15 P 1.3
14 P 1.2
13 P 1.1
12 P 1.0
11 P 3.7
Specifications subject to change without notice, contact your sales representatives for the most recent information.
1/27
PID256** 07/97






MV20556 Datasheet, Funktion
MOSEL VITELIC INC.
Preliminary
MV20556
Memory Map Details
Internal RAM
The MV20556 contains a 128-byte Internal Data RAM
(Which includes registers R7-R0 in each of four Banks),
and twenty memory-mapped Special Function
Registers.
Internal Data RAM
The Internal Data RAM provides a convenient 128-byte
scratch pad memory.
128 Addressable Bits
There are 128 addressable software flags in the
Internal Data RAM. They are located in the 16 byte
locations starting at byte address 32 and ending with
byte location 47 of the RAM address space.
Stack
The stack may be located anywhere within the Internal
Data RAM address space. The stack may be as large
as 128 bytes on the MV20556.
Register Banks
There are four Register Banks within the Internal Data
RAM. Each Register Bank contains registers R7-R0.
7Fh
RAM
BYTE (MSB)
7FH
(LSB)
127
2FH 7F 7E 7D 7C 7B 7A 79 78 47
2EH 77 76 75 74 73 72 71 70 46
2DH 6F 6E 6D 6C 6B 6A 69 68 45
2CH 67 66 65 64 63 62 61 60 44
2BH 5F 5E 5D 5C 5B 5A 59 58 43
2AH 57 56 55 54 53 52 51 50 42
29H 4F 4E 4D 4C 4B 4A 49 48 41
28H 47 46 45 44 43 42 41 40 40
27H 3F 3E 3D 3C 3B 3A 39 38 39
26H 37 36 35 34 33 32 31 30 38
25H 2F 2E 2D 2C 2B 2A 29 28 37
24H 27 26 25 24 23 22 21 20 36
23H 1F 1E 1D 1C 1B 1A 19 18 35
22H 17 16 15 14 13 12 11 10 34
21H 0F 0E 0D 0C 0B 0A 09 08 33
20H 07 06 05 04 03 02 01 00 32
1FH
18H Bank 3
31
23
17H 24
Bank 2
10H
16
0FH 15
Bank 1
08H
8
07H 7
Bank 0
00H
0
scratch
pad
area
30h
2Fh
bit
addressable
area
RS1 RS0
R7
11
R0
R7
10
R0
R7
01
R0
R7
00
R0
20h
1Fh
18h
17h
Four
10h
0Fh
bank
area
08h
07h
00h
128B RAM Bit Address
128B RAM Memory Map
Specifications subject to change without notice, contact your sales representatives for the most recent information.
6/27
PID256** 07/97

6 Page









MV20556 pdf, datenblatt
MOSEL VITELIC INC.
Preliminary
Interrupt System (Cont'd)
that occurs fourteen oscillator periods before the end of
the instruction in progress, an interrupt subroutine call
is made. The level-activated input need be low only
during the sampling that occurs fourteen oscillator
periods before the end of the instruction-in-progress
and may remain low during the entire execution of the
service program. However, the input must be raised
before the service program completes to avoid possible
envoking a second interrupt.
MV20556
MSB
LSB
- - - PS PT1 PX1 PT0 PX0
- IP.7 Reserve for future use.
- IP.6 Reserve for future use.
- IP.5 Reserve for future use.
PS IP.4 Serial Port Priority control bit. Set/cleared by software to specify high/low priority interrupts for Serial
port.
PT1 IP.3 Defines the idle or power down mode interrupt priority level. Set/cleared by software to specify high/low
priority interrupts for timer/counter1.
PX0 IP.2 External interrupt 1 Priority control bit. Set/cleared by software to specify high/low priority interrupts for
INT1.
PT0 IP.1 Defines the timer 0 interrupt priority level. Set/cleared by software to specify high/low priority interrupts
for timer/counter0.
PX1 IP.0 External interrupt 0 Priority control bit. Set/cleared by software to specify high/low priority interrupts for
INT0.
IP definition
Specifications subject to change without notice, contact your sales representatives for the most recent information.
12/27
PID256** 07/97

12 Page





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