ZR36015 Datasheet PDF - ZORAN
| Part Number | ZR36015 | |
| Description | RASTER TO BLOCK CONVERTER | |
| Manufacturers | ZORAN | |
| Logo |  |
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PRELIMINARY
FEATURES
s Real Time Raster to/from Block Conversion
s 1/2 Decimation Processing in the Horizontal Direction
s 30 MHz Maximum Clock Rate
s Only Image in Preset Window is Converted
s Compatable with Zorans ZR36050 JPEG Coder and
ZR36011 Color Space Converter
ZR36015
RASTER TO BLOCK CONVERTER
s Supports 1:0:0,4:2:2,and 4:1:1 data formats
s 100-pin plastic quad flat package (PQFP)
s TTL level Input/Output
s Synchronous data and controls
s Low power consumption: 0.45W (Typ.)
s CMOS circuit operating with a single 5V power supply
APPLICATIONS
s Image processing
s Multi-media
s Scanners
s Image Storage
s Image Capture
DESCRIPTION
The ZR36015 performes raster to/from block conversion for
image compression and expansion applications, and it can be
connected directly to the ZR36050 JPEG coder and the
ZR36011 Color Space Converter.
An image compression system can be easily constructed using
the ZR36015 with the ZR35060 and ZR36011.
The ZR36015 uses a double buffered external SRAM Strip
Buffer to support raster to/from block conversion and block inter-
leave.
The maximum number of pixels that can be processed per line
is 8K. The maximum number of lines that can be prcessed per
image is 16K. These numbers vary according to the mode of
operation.
The ZR36015 supports 4:0:0, 4:1:1, and 4:2:2 data formats, and
one half decimation in horizontal direction during compression.
The maximum data transfer rate to the ZR36050 coder is 30
MHz.
[The ZR36015 is fabricated with an advanced low-power CMOS
technology, making it suitable for use in low-power, cost sensi-
tive applications. The device is availiable in a 100 pin , Plastic
Quad Flat Package (PQFP).]
Host Interface
SPH WR
RD ADD(1:0)
CBSY
PXDATA(15:0)
Pixel
Interface
HEN
VEN
WINDOW
BSY
CLKCSC
Internal Register Control
Raster/Block
Address
Generator
1/2
Decimation
Window
Control
Interface Logic
I/F
DSYNC
EOS
STOP
COE
BDATA(7:0)
Coder Interface
MWE
MOE
MADD(15:0)
Memory
Interface
MDATA(15:0)
RESET
SYSCLK
Pixel
Interface
8
PXDATA(15:0)
MWE
CBUSY
HEN
VEN
WINDOW
BSY
MOE
MADD(15:0)
16
16
MDATA(15:0)
CLKCSC
Host
Interface
System
Clock
System
Reset
SPH
RD
WR
2 ADD(1:0)
SYSCLK
RESET
8
BDATA(7:0)
COE
EOS
STOP
DSYNC
Memory
Interface
Coder
Interface
Figure 1. ZR36015 Block Diagram
Figure 2. ZR36015 Logical Pinout
ZORAN Corporation s 1705 Wyatt Drive s Santa Clara, CA 95054 s (408) 986-1314 s FAX (408) 986-1240
June 1993
This document was created with FrameMaker 4.0.4
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PRELIMINARY
ZR36015
s VHeight(12:0):Verticle height of the active image area. The
maximum setting for Height(12:0) is 8191. Setting
Height(12:0) to ‘0’ in encode mode, lets the Height of the
active image area be determined by the non-active point of
VEN.
Address Pointer Value
Window Setting Value
0 HDelay(7:0)
1 HDelay(12:8)1
2 HWidth(7:0)
3 HWidth(14:0)1
4 VDelay(7:0)
5 VDelay(12:8)1
6 VWidth(7:0)
7 VWidth(13:8)1
8 Number of Lines(7:0)
9 Number of Lines(13:8)1
1. Assigned to LSB’s of PIXDATA(7:0)
HEN
Enable Area
HDelay
Acitve Image
Area
HWidth
Figure 4. Active Image Area
Number of Lines Table:
The Number of Lines Table holds the number of lines processed
in encoding by the ZR36015.
Operating States
The ZR36015 has four Operating States; Reset, Idle, Compres-
sion and Expansion.
Reset State
While the RESET input is asserted, the ZR36015 is in the Reset
State. In this state the PXDATA and BDATA busses are high
impedance, and the DSYNC, STOP, EOS signals are high
impedance.
After a RESET, the ZR36015 will be in the IDLE state.
Idle State
After a Soft RESET, or after the RESET input signal has been
applied, or at the end of a compression or expansion process,
the ZR36015 will be in the IDLE state. In the IDLE state, no
active processing is taking place, and the PXDATA bus is high
impedance (the bus drivers for the Coder Interface are con-
trolled by the COE signal).
While in the IDLE state, the ZR36015 Configuration Register
Tables can be loaded with the values to select the desired active
image area. Also, the Mode Register is loaded with the desired
Mode of operation, and the number of lines table can be read
To leave the IDLE state and enter one of the processing states
(compression or expansion), the GO bit in the Mode registe is
set.
Compression
When the GO bit is set to “1”, and the EDC bit equals “1”, then
the ZR36015 enters the Compression State.
Setting the GO bit results in the BSY bit in the mode register
being set.
Once the GO bit is set, then on the falling edge of the Verticle
Sync Signal (VEN), the BSY output signal will be set. The BSY
bit (and output signal) will stay set until the end of the Compres-
sion process. The hardware can monitor the BSY signal, to
determine when the Compression process has completed. Note
that the GO bit must be set at least three SYSCLK cycles before
the VEN goes from High to Low (see figure ???).
Following the above, the ZR36015 monitors the VEN input to
detect the transiton of VEN from low to high. This indicates the
beginning of the image to be processed The next VDelay lines
of data are ignored in order to reach the “active image area”.
Then the next VWidth lines of data are processed.
The HEN input synchronizes the line by line transfers of data into
the ZR36015. On the rise of HEN, the next HDelay pixels are
ignored in order to reach the “active image area”. Then the next
HWidth pixels are procesed.
5
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Part DetailsOn this page, you can learn information such as the schematic, equivalent, pinout, replacement, circuit, and manual for ZR36015 electronic component. |
| Information | Total 27 Pages | |
| Link URL | [ Copy URL to Clipboard ] | |
| Download | [ ZR36015.PDF Datasheet ] | |
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