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PDF MC7445 Data sheet ( Hoja de datos )
| Número de pieza | MC7445 | |
| Descripción | RISC Microprocessor Hardware Specifications | |
| Fabricantes | Freescale Semiconductor | |
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Freescale Semiconductor
Technical Data
MPC7455EC
Rev. 4.1, 02/2005
MPC7455
RISC Microprocessor
Hardware Specifications
The MPC7455 and MPC7445 are implementations of the
PowerPC™ microprocessor family of reduced instruction set
computer (RISC) microprocessors. This document is primarily
concerned with the MPC7455; however, unless otherwise noted,
all information here also applies to the MPC7445. This document
describes pertinent electrical and physical characteristics of the
MPC7455. For functional characteristics of the processor, refer to
the MPC7450 RISC Microprocessor Family User’s Manual. To
locate any published updates for this document, refer to the
website at http://www.freescale.com.
1 Overview
The MPC7455 is the third implementation of the fourth generation
(G4) microprocessors from Freescale. The MPC7455 implements
the full PowerPC 32-bit architecture and is targeted at networking
and computing systems applications. The MPC7455 consists of a
processor core, a 256-Kbyte L2, and an internal L3 tag and
controller which support a glueless backside L3 cache through a
dedicated high-bandwidth interface. The MPC7445 is identical to
the MPC7455 except it does not support the L3 cache interface.
Figure 1 shows a block diagram of the MPC7455.
Contents
1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2. Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3. Comparison with the MPC7400, MPC7410,
MPC7450, MPC7451, and MPC7441 . . . . . . . . . . . . . 7
4. General Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5. Electrical and Thermal Characteristics . . . . . . . . . . . 10
6. Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
7. Pinout Listings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
8. Package Description . . . . . . . . . . . . . . . . . . . . . . . . . 41
9. System Design Information . . . . . . . . . . . . . . . . . . . 45
10. Document Revision History . . . . . . . . . . . . . . . . . . . 59
11. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . 60
© Freescale Semiconductor, Inc., 2005. All rights reserved.
1 page  
Features
— Retires as many as three instructions per clock cycle
• Separate on-chip L1 instruction and data caches (Harvard architecture)
— 32-Kbyte, eight-way set-associative instruction and data caches
— Pseudo least-recently-used (PLRU) replacement algorithm
— 32-byte (eight-word) L1 cache block
— Physically indexed/physical tags
— Cache write-back or write-through operation programmable on a per-page or per-block basis
— Instruction cache can provide four instructions per clock cycle; data cache can provide four words per
clock cycle
— Caches can be disabled in software
— Caches can be locked in software
— MESI data cache coherency maintained in hardware
— Separate copy of data cache tags for efficient snooping
— Parity support on cache and tags
— No snooping of instruction cache except for icbi instruction
— Data cache supports AltiVec LRU and transient instructions
— Critical double- and/or quad-word forwarding is performed as needed. Critical quad-word forwarding
is used for AltiVec loads and instruction fetches. Other accesses use critical double-word forwarding.
• Level 2 (L2) cache interface
— On-chip, 256-Kbyte, eight-way set-associative unified instruction and data cache
— Fully pipelined to provide 32 bytes per clock cycle to the L1 caches
— A total nine-cycle load latency for an L1 data cache miss that hits in L2
— PLRU replacement algorithm
— Cache write-back or write-through operation programmable on a per-page or per-block basis
— 64-byte, two-sectored line size
— Parity support on cache
• Level 3 (L3) cache interface (not implemented on MPC7445)
— Provides critical double-word forwarding to the requesting unit
— Internal L3 cache controller and tags
— External data SRAMs
— Support for 1- and 2-Mbyte L3 caches
— Cache write-back or write-through operation programmable on a per-page or per-block basis
— 64-byte (1M) or 128-byte (2M) sectored line size
— Private memory capability for half (1-Mbyte minimum) or all of the L3 SRAM space
— Supports MSUG2 dual data rate (DDR) synchronous Burst SRAMs, PB2 pipelined synchronous Burst
SRAMs, and pipelined (register-register) late write synchronous Burst SRAMs
— Supports parity on cache and tags
— Configurable core-to-L3 frequency divisors
— 64-bit external L3 data bus sustains 64 bits per L3 clock cycle
MPC7455 RISC Microprocessor Hardware Specifications, Rev. 4.1
Freescale Semiconductor
5
5 Page 
Figure 2 shows the undershoot and overshoot voltage on the MPC7455.
OVDD/GVDD + 20%
OVDD/GVDD + 5%
OVDD/GVDD
Electrical and Thermal Characteristics
VIH
VIL
GND
GND – 0.3 V
GND – 0.7 V
Not to Exceed 10%
of tSYSCLK
Figure 2. Overshoot/Undershoot Voltage
The MPC7455 provides several I/O voltages to support both compatibility with existing systems and migration to
future systems. The MPC7455 core voltage must always be provided at nominal 1.3 V (see Table 4 for actual
recommended core voltage). Voltage to the L3 I/Os and processor interface I/Os are provided through separate sets
of supply pins and may be provided at the voltages shown in Table 3. The input voltage threshold for each bus is
selected by sampling the state of the voltage select pins at the negation of the signal HRESET. The output voltage
will swing from GND to the maximum voltage applied to the OVDD or GVDD power pins.
Table 3. Input Threshold Voltage Setting
BVSEL Signal
Processor Bus Input
Threshold is Relative to:
L3VSEL Signal 5
L3 Bus Input Threshold is
Relative to:
Notes
0
1.8 V
0
1.8 V
1, 4
¬HRESET
Not Available
¬HRESET
1.5 V
1, 3
HRESET
2.5 V
HRESET
2.5 V
1, 2
1
2.5 V
1
2.5 V
1
Notes:
1. Caution: The input threshold selection must agree with the OVDD/GVDD voltages supplied. See notes in Table 2.
2. To select the 2.5-V threshold option for the processor bus, BVSEL should be tied to HRESET so that the two signals
change state together. Similarly, to select 2.5 V for the L3 bus, tie L3VSEL to HRESET. This is the preferred method
for selecting this mode of operation.
3. Applicable to L3 bus interface only. ¬HRESET is the inverse of HRESET.
4. If used, pulldown resistors should be less than 250 Ω.
5. Not implemented on MPC7445.
MPC7455 RISC Microprocessor Hardware Specifications, Rev. 4.1
Freescale Semiconductor
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet MC7445.PDF ] | |
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