PDF MX66C1024 Data sheet ( Hoja de datos )

Número de pieza	MX66C1024
Descripción	5V Low Power CMOS SRAM 128 x 8 Bit
Fabricantes	Macronix International
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No Preview Available ! n FEATURES • Vcc operation voltage : 5V • Low power consumption : 45mA (Max.) write current 2mA (Max.) read current 0.6uA (Typ.) CMOS standby current • High speed access time : -70 70ns (Max.) -10 100ns (Max.) • Input levels are CMOS-compatible • Automatic power down when chip is deselected • Three state outputs • Fully static operation • Data retention supply voltage as low as 1.2V • Easy expansion with CE2, CE1, and OE options n PIN CONFIGURATIONS NC A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 GND 1 32 2 31 3 30 4 29 5 28 6 27 7 26 8 MX66C1024MC 25 9 MX66C1024MI 24 10 23 11 22 12 21 13 20 14 19 15 18 16 17 VCC A15 CE2 WE A13 A8 A9 A11 OE A10 CE1 DQ7 DQ6 DQ5 DQ4 DQ3 A11 A9 A8 A13 WE CE2 A15 VCC NC A16 A14 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 MX66C1024TC MX66C1024SC MX66C1024TI MX66C1024SI 32 OE 31 A10 30 CE1 29 DQ7 28 DQ6 27 DQ5 26 DQ4 25 DQ3 24 GND 23 DQ2 22 DQ1 21 DQ0 20 A0 19 A1 18 A2 17 A3 MX66C1024 5V Low Power CMOS SRAM 128 x 8 Bit n DESCRIPTION The MX66C1024 is a high performance, extremely low power CMOS Static Random Access Memory organized as 131,072 words by 8 bits and operates at 5.0V supply voltage. Advanced CMOS technology and circuit techniques provide both high speed and low power features with a typical CMOS standby current of 0.005uA and maximum access time of 70ns and 100ns Easy memory expansion is provided by an active LOW chip enable (CE1), an active HIGH chip enable (CE2), and active LOW output enable (OE) and three-state output drivers. The MX66C1024 has an automatic power down feature, reducing the power consumption significantly when chip is deselected. The MX66C1024 is available in the JEDEC standard 32 pin SOP, STSOP and TSOP. n BLOCK DIAGRAM A6 A7 A12 A14 A16 A15 A13 A8 A9 A11 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 CE2 CE1 WE OE Vdd Gnd Address Input Buffer 20 Row Decoder 1024 Memory Array 1024 x 1024 8 8 Control Data Input Buffer Data Output Buffer 1024 8 Column I/O Write Driver Sense Amp 8 128 Column Decoder 14 Address Input Buffer A5 A4 A3 A2 A1 A0 A10 P/N DS00040 1 Macronix America Inc., USA 1338 Ridder Park Dr., San Jose, CA 95131 Tel (408)453-8088 Fax (408)451-0876 http: www.macronix.com Rev. 1.0, November 1999 1 page n SWITCHING WAVEFORMS (READ CYCLE) READ CYCLE1 (1,2,4) ADDRESS D OUT t OH t AA t RC MX66C1024 t OH READ CYCLE2 (1,3,4) CE1 t ACS1 CE2 D OUT t ACS2 (5) t CLZ READ CYCLE3 (1,4) ADDRESS OE CE1 CE2 D OUT t RC t AA t OE t OLZ t(5) ACS1 t CLZ1 t ACS2 (5) t CLZ2 NOTES: 1. WE is high for read Cycle. 2. Device is continuously selected when CE1 = VIL and CE2= VIH. 3. Address valid prior to or coincident with CE1 transition low and/or CE2 transition high. 4. OE = VIL . 5. Transition is measured ± 500mV from steady state with CL = 5pF as shown in Figure 1B. The parameter is guaranteed but not 100% tested. (5) t CHZ t OH t (5) OHZ (1,5) t CHZ (2,5) t CHZ P/N DS00040 5 Macronix America Inc., USA 1338 Ridder Park Dr., San Jose, CA 95131 Tel (408)453-8088 Fax (408)451-0876 http: www.macronix.com Rev. 1.0, November 1999 5 Page

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