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PDF ST72E331 Data sheet ( Hoja de datos )
| Número de pieza | ST72E331 | |
| Descripción | 8-BIT MCU WITH 8 TO 16K OTP/EPROM | |
| Fabricantes | ST Microelectronics | |
| Logotipo |  |
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ST72E331
ST72T331
8-BIT MCU WITH 8 TO 16K OTP/EPROM, 256 EEPROM,
384 TO 512 BYTES RAM, ADC, WDG, SCI, SPI AND 2 TIMERS
DATASHEET
s User Program Memory (OTP/EPROM):
8 to 16K bytes
s User EEPROM: 256 bytes
s Data RAM: 384 to 512 bytes including 256 bytes
of stack
s Master Reset and Power-On Reset
s Low Voltage Detector (LVD) Reset option
s Run and Power Saving modes
s 44 or 32 multifunctional bidirectional I/O lines:
– 15 or 9 programmable interrupt inputs
– 8 or 4 high sink outputs
– 8 or 6 analog alternate inputs
– 13 alternate functions
– EMI filtering
s Software or Hardware Watchdog (WDG)
s Two 16-bit Timers, each featuring:
– 2 Input Captures 1)
– 2 Output Compares 1)
– External Clock input (on Timer A)
– PWM and Pulse Generator modes
s Synchronous Serial Peripheral Interface (SPI)
s Asynchronous Serial Communications Interface
(SCI)
s 8-bit ADC with 8 channels 2)
s 8-bit Data Manipulation
s 63 basic Instructions and 17 main Addressing
Modes
s 8 x 8 Unsigned Multiply Instruction
s True Bit Manipulation
s Complete Development Support on DOS/
WINDOWSTM Real-Time Emulator
s Full Software Package on DOS/WINDOWSTM
(C-Compiler, Cross-Assembler, Debugger)
Device Summary
PSDIP42
CSDIP42W
PSDIP56
CSDIP56W
TQFP64
TQFP44
(See ordering information at the end of datashee
Notes:
1. One only on Timer A.
2. Six channels only for ST72T331J.
Features
ST72T331J2
ST72T331J4
ST72T331N2
ST72T331N4
Program Memory - bytes
EEPROM - bytes
RAM (stack) - bytes
Peripherals
Operating Supply
CPU Frequency
Temperature Range
Package
8K 16K 8K 16K
256
384 (256)
512 (256)
384 (256)
512 (256)
Watchdog, Timers, SPI, SCI, ADC and optional Low Voltage Detector Reset
3 to 5.5 V
8MHz max (16MHz oscillator) - 4MHz max over 85°C
- 40°C to + 125°C
TQFP44 - SDIP42
TQFP64 - SDIP56
Note: The ROM versions are supported by the ST72334 family.
Rev. 1.7
September 1999
1/106
1
1 page  
ST72E331 ST72T331
1 GENERAL DESCRIPTION
1.1 INTRODUCTION
The ST72T331 HCMOS Microcontroller Unit
(MCU) is a member of the ST7 family. The device
is based on an industry-standard 8-bit core and
features an enhanced instruction set. The device
is normally operated at a 16 MHz oscillator fre-
quency. Under software control, the ST72T331
may be placed in either Wait, Slow or Halt modes,
thus reducing power consumption. The enhanced
instruction set and addressing modes afford real
programming potential. In addition to standard
8-bit data management, the ST72T331 features
true bit manipulation, 8x8 unsigned multiplication
and indirect addressing modes on the whole mem-
ory. The device includes a low consumption and
Figure 1. ST72T331 Block Diagram
fast start on-chip oscillator, CPU, program memo-
ry (OTP/EPROM versions), EEPROM, RAM, 44
(QFP64 and SDIP56) or 32 (QFP44 and SDIP42)
I/O lines, a Low Voltage Detector (LVD) and the
following on-chip peripherals: Analog-to-Digital
converter (ADC) with 8 (QFP64, SDIP56) or 6
(QFP44, SDIP42) multiplexed analog inputs, in-
dustry standard synchronous SPI and asynchro-
nous SCI serial interfaces, digital Watchdog, two
independent 16-bit Timers, one featuring an Exter-
nal Clock Input, and both featuring Pulse Genera-
tor capabilities, 2 Input Captures and 2 Output
Compares (only 1 Input Capture and 1 Output
Compare on Timer A).
OSC IN
OSCOU T
R ESE T
PF0 -> PF2,4,6,7
(6 bits)
VDD
VSS
OSC
Internal
CLOCK
CONTROL
AND LVD
8-BIT CORE
ALU
PROGRAM
MEMORY
(8 - 16K Bytes)
EEPROM
(256 Bytes)
RA M
(384 - 512 Bytes)
PORT F
TIMER A
POWER
SUP PLY
PORT A
PORT B
TIMER B
PORT C
SPI
PORT D
8-BIT ADC
PORT E
SCI
WATCH DOG
PA0 -> PA7
(8 bits for ST72T331N)
(5 bits for ST72T331J)
PB0 -> PB7
(8 bits for ST72T331N)
(5 bits for ST72T331J)
PC0 -> PC7
(8 bits)
PD0 -> PD7
(8 bits for ST72T331N)
(6 bits for ST72T331J)
PE0 -> PE7
(6 bits for ST72T331N)
(2 bits for ST72T331J)
VDDA
VSSA
5/106
5
5 Page 
ST72E331 ST72T331
1.4 MEMORY MAP
Figure 7. Program Memory Map
0000h
007Fh
0080h
01FFh
HW Registers
(see Table 4)
384 Bytes RAM
027Fh
512 Bytes RAM
0200h / 0280h
0BFF h
0C00h
0CFFh
0D00h
BFFFh
C000h
E000h
FFDFh
Reserved
256 Bytes EEPROM
Reserved
8K Bytes
Program
Memory
16K Bytes
Program
Memory
FFE 0h
Interrupt & Reset Vectors
FFFF h
(see Table 3)
0080h
00FFh
Short Addressing
RAM (zero page)
0100h 256 Bytes Stack/
01FFh 16-bit Addressing RAM
0080h
00FFh
Short Addressing
RAM (zero page)
0100h
256 Bytes Stack/
16-bit Addressing RAM
01FFh
0200h
027Fh
16-bit Addressing
RAM
Table 3. Interrupt Vector Map
Vector Address
FF E0-FFE1h
FF E2-FFE3h
FF E4-FFE5h
FF E6-FFE7h
FF E8-FFE9h
FF EA-FF EBh
FF EC-FFE Dh
FF EE-FFE Fh
FF F0-FF F1h
FF F2-FF F3h
FF F4-FF F5h
FF F6-FF F7h
FF F8-FF F9h
FFFA-FF FBh
FF FC-FF FDh
FF FE-FF FFh
Description
Not Used
Not Used
EEPROM Interrupt Vector
SCI Interrupt Vector
TIMER B Interrupt Vector
TIMER A Interrupt Vector
SPI interrupt vector
Not Used
External Interrupt Vector EI3
External Interrupt Vector EI2
External Interrupt Vector EI1
External Interrupt Vector EI0
Not Used
Not Used
TRAP (software) Interrupt Vector
RESET Vector
Remarks
Internal Interrupt
Internal Interrupt
Internal Interrupt
Internal Interrupt
Internal Interrupt
External Interrupt
External Interrupt
External Interrupt
External Interrupt
CPU Interrupt
11/106
11
11 Page | ||
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