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IR1110 Schematic ( PDF Datasheet ) - International Rectifier

Teilenummer IR1110
Beschreibung SOFT START CONTROLLER IC
Hersteller International Rectifier
Logo International Rectifier Logo 




Gesamt 30 Seiten
IR1110 Datasheet, Funktion
ADVANCE INFORMATION Data Sheet No. PD60164A
IR1110
SOFT START CONTROLLER IC
Features
Product Summary
Self-contained soft charging of DC bus capacitor
DC bus voltage regulation
3-phase or 1-phase AC input
Applicable to 115/230/380/460/575V AC input
Drives SCR phase controlled half bridge
Programmable ramp rate
Protection against DC bus short circuit
Fast power dip ride through with automatic ramp back
Selectable shutdown on single phase loss
1-phase and 3-phase loss fault output
VDDS/VSS
ISS/IDD
+/- 5V
+/- 5mA
DC bus registration
response time
100msec (typ.)
Min. DC bus regulation 35% of VDCMAX
voltage with capacitive load
Insensitive to phase rotation
High line or low line fault output
Low power consumption
Programmable
DC bus ramp time
100msec to
330msec (typ.)
Integrated watchdog function for each phase
64-pin MQFP package
Description
The IR1110 is a high performance analog IC designed
to control ramp rate and voltage of the DC bus from
Typical Application
Motor drives
Welders
Battery chargers
Power supplies
either single or three phase AC line voltage input. It con- Package
trols a SCR half bridge and provides robust ride through
capability in event of transient loss of line, and DC bus
regulation with eternal reference input. Comprehensive
line status fault output including 1/3 phase loss and high
or low line fault provides versatile line diagnostic capa-
bility to the system. The IR1110 is based on advanced
low power design so it can utilize the SCR snubber
derived power supply.
64 Lead MQFP
System Block Diagram
Snubber and
Snubber derived
power supply
IR1110
and
Peripheral
Components
AC
3-Phase
Input
(Optional)
+
(Optional)
-






IR1110 Datasheet, Funktion
IR1110
ADVANCE INFORMATION
Notes for DC Electrical Characteristics
Note 1) VBREF=5.0V will assure full SCR firing on to produce the maximum amount of DC bus voltage and faster conver-
gence to the maximum DC bus voltage. Although VBREF=4.0V corresponds to the maximum voltage, it will take longer time
to converge to the maximum DC bus voltage.
Note 2) These voltage values are linearly proportional to VLNSET. For example, if VLNSET = 2.0V, then all values are twice
of those values listed in the table.
Note 3) VDD must be regulated within ±2.5%. VSS must be regulated within ±5%.
AC Electrical Characteristics
VDD = 5.1V, VSS, = 5.1V, CL = 1000pF and TA = 25°C unless otherwise specified.
Symbol
tr
tf
tWSCR
tDLL
Definition
Turn-on rise time on SCRU, SCRV, and SCRW
Turn-off fall time on SCRU, SCRV, and SCRW
Output pulse width of SCRU,SCRV, and SCRW
LNLSLED propagation delay
tD1PH
tLN
tS1PH
1PHLED propagation delay
LNLED propagation delay
Shutdown time after loss of single phase
tfFO
tW1PH
Fall time from high to low on LNLSLED,
1PHLED, LNLED
1PHLED pulse width
tUVLCK Power up UVLOCK delay
tRAMP DC bus ramp time
VENSCR
PPUBAL
Minimum input voltage on UIN, VIN, and WIN
for enabling SCR firing
Phase-to-phase unbalance between
pulses on SCRU, SCRV, and SCRW
See Notes on page 7
Min. Typ. Max. Units Test Conditions
—- 500 —-
ns
—- 500 —-
—- 15 —- µs
—- 30 —-
LNLSSL=VDD,
C3PH =.022uF,
—- 8.3 —- ms
(note 1)
C1PH = .001uF
—- 150 —-
—- 15 20 ms
(note 2)
1PHEN = VDD,
CUVLO = .1mF,
C1PH = .001mF,
—- 50 —- ns
(note 3)
Pull-up resistor
= 6.2kW
—- 2 —-
C1PH =.001mF,
(note 4)
60 msec CUVLCK=.1uF,
(note 5)
150 CRAMP=1uF,
—- RU2/RU1 —-
X 12
—- ±1.5 —-
RRAMP=82k,(note 6)
V (note 7)
Firing angle = 90°
—- ±3 —-
Notes 8 and 9
o
° Firing angle = 140°
Note 9
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6 Page









IR1110 pdf, datenblatt
IR1110
Lead Definitions
Symbol
DVDD
DGND
DVSS
AVDD
AGND
AVSS
UIN/VIN/WIN
VBAMPP
VBAMPN
VBUSO
VBREF
DCREG2
DCREG1
DCREGC
1PHSEL
1PHEN
LNLSSL
1PHCAP
3PHCAP
VRAMP
RAMPERR
CRAMP
RRAMP
RBIAS
VPKLL
UVLOCAP
BDIP1
BDIP2
BDIPHLD
BDIPCAP
VPKDISC1
VPKDISC2
VPK
VPKREC
WDCAPU/V/W
LNSET
LNLSLED
1PHLED
LNLED
CINTU/V/W
INTNU/V/W
RINTU/V/W
RSTRU/V/W
SCRU/V/W
TEST1
TEST2
SCRREF
Pin #
44
43
31
17
25,26,43
4,31,51
1,2,3
5
6
7
8
9
11
10
12
13
14
15
16
18
19
20
21
22
23
24
29
27
30
28
33
32
34
35
38,37,36
39
40
41
42
61,57,53
62,58,54
63,59,55
64,60,56
47,46,45
48
49
50
12
ADVANCE INFORMATION
Description
Logic positive supply voltage.
Logic ground
Logic negative supply voltage
Analog positive supply voltage
Analog ground
Analog negative supply voltage
Phase U/V/W voltage inputs
DC bus OP Amp. positive input, connect to DC bus(-) via resistor
DC bus OP Amp. negative input, connect to DC bus (+) via resistor
DC bus OP Amp. output
DC bus regulation voltage reference input
DC bus error amplifier output via series diode
DC bus error amplifier output
DC bus error compensation (External capacitor connection pin)
Single phase input mode select.
Note 1) on page 12
Single phase shutdown mode enable.
Note 2) on page 12
Phase loss Fault Output Select.
Note 3) on page 12
Single phase loss detect timing capacitor
Three phase loss detect timing capacitor
Buffered voltage ramp circuit output
Ramp error amplifier input
Ramp timing capacitor
Ramp timing resistor
Bias current resistor
Line-to-line peak voltage holding capacitor
Under voltage lockout delay capacitor
DC bus voltage dip detection 1
DC bus voltage dip detection 2
DC bus voltage dip hold capacitor
DC bus voltage dip timing capacitor
Line synchronization timing wave peak voltage discharging resistor
No connection
Line synchronization timing wave peak voltage
Line synchronization timing waveform
Watchdog timing capacitor for phase U, V, and W
Line voltage comparator reference input
Line Loss Fault Output
Single Phase Loss Fault Output
High/Low line status Output
Phase U/V/W integral amplifier output
Phase U/V/W integral amplifier negative input
Phase U/V/W integral amplifier resistor connection
Phase U/V/W integral discharge resistor
Phase U/V/W SCR gate signal
Test purpose pin (Should be tied to VDD)
Test purpose pin (No connection should be made)
SCR gate signal reference
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