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PDF SY100E143 Data sheet ( Hoja de datos )
| Número de pieza | SY100E143 | |
| Descripción | 9-BIT HOLD REGISTER | |
| Fabricantes | Micrel Semiconductor | |
| Logotipo |  |
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9-BIT HOLD
REGISTER
SY10E143
SY100E143
FEATURES
s 700MHz min. operating frequency
s Extended 100E VEE range of –4.2V to –5.5V
s 9 bits wide for byte-parity applications
s Asynchronous Master Reset
s Dual clocks
s Fully compatible with industry standard 10KH,
100K ECL levels
s Internal 75kΩ input pulldown resistors
s Fully compatible with Motorola MC10E/100E143
s Available in 28-pin PLCC package
BLOCK DIAGRAM
MUX
D0
D1 MUX
MUX
D2
MUX
D3
D4 MUX
MUX
D5
D6 MUX
D7 MUX
D8
SEL
CLK1
CLK2
MR
MUX
D
R
D
R
D
R
D
R
D
R
D
R
D
R
D
R
D
R
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
DESCRIPTION
The SY10/100E143 are high-speed 9-bit hold registers
designed for use in new, high-performance ECL systems.
The E143 can hold current data or load new data. The nine
inputs, D0-D8, accept parallel input data.
The SEL (Select) control pin serves to determine the
mode of operation; either HOLD or LOAD. The input data
has to meet the set-up time before being clocked into the
nine input registers on the rising edge of CLK1 or CLK2.
The MR (Master Reset) control signal asynchronously
resets all nine registers to a logic LOW when a logic HIGH
is applied to MR.
The E143 is designed for applications requiring high-
speed registers, pipeline registers, synchronous operation,
and is also suitable for byte-wide parity.
PIN CONFIGURATION
MR
CLK1
CLK2
VEE
NC
D0
D1
25 24 23 22 21 20 19
26 18
27 17
28
PLCC
16
1
TOP VIEW
15
2
J28-1
14
3 13
4 12
5 6 7 8 9 10 11
Q7
Q6
VCC
Q5
VCCO
Q4
Q3
PIN NAMES
Pin
D0-D8
SEL
CLK1, CLK2
MR
Q0-Q8
NC
VCCO
1
Function
Parallel Data Inputs
Mode Select Input
Clock Inputs
Master Reset
Data Outputs
No Connection
VCC to Output
Rev.: D Amendment: /0
Issue Date: August, 1998
1 page | ||
| Páginas | Total 4 Páginas | |
| PDF Descargar | [ Datasheet SY100E143.PDF ] | |
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