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PDF SY100E196 Data sheet ( Hoja de datos )
| Número de pieza | SY100E196 | |
| Descripción | PROGRAMMABLE DELAY CHIP WITH ANALOG INPUT | |
| Fabricantes | Micrel Semiconductor | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de SY100E196 (archivo pdf) en la parte inferior de esta página. Total 9 Páginas | ||
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PROGRAMMABLE DELAY
CHIP WITH ANALOG INPUT
ClockWorks™
SY10E196
SY100E196
FEATURES
s Up to 2ns delay range
s Extended 100E VEE range of –4.2V to –5.5V
s ≈20ps digital step resolution
s Linear input for tighter resolution
s >1GHz bandwidth
s On-chip cascade circuitry
s 75KkΩ input pulldown resistor
s Fully compatible with Motorola MC10E/100E196
s Available in 28-pin PLCC package
PIN CONFIGURATION
D1
D0
LEN
VEE
IN
IN
VBB
25 24 23 22 21 20 19
26 18
27 17
28 TOP VIEW 16
1
PLCC
15
2
J28-1
14
3 13
4 12
5 6 7 8 9 10 11
FTUNE
NC
VCC
VCCO
Q
Q
VCCO
DESCRIPTION
The SY10/100E196 are programmable delay chips
(PDCs) designed primarily for very accurate differential
ECL input edge placement applications.
The delay section consists of a chain of gates and a
linear ramp delay adjustment organized as shown in the
logic diagram. The first two delay elements feature gates
that have been modified to have delays 1.25 and 1.5
times the basic gate delay of approximately 80ps. These
two elements provide the E196 with a digitally-selectable
resolution of approximately 20ps. The required device
delay is selected by the seven address inputs D[0:6],
which are latched on-chip by a high signal on the latch
enable (LEN) control. If the LEN signal is either LOW or
left floating, then the latch is transparent.
The FTUNE input takes an analog coltage and applies
it to an internal linear ramp for reducing the 20s resolution
still further. The FTUNE input is what differentiates the
E196 from the E195.
An eighth latched input, D7, is provided for cascading
multiple PDCs for increased programmable range. The
cascade logic allows full control of multiple PDCs, at the
expense of only a single added line to the data bus for
each additional PDC, without the need for any external
gating.
PIN NAMES
Pin
IN/IN
EN
D[0:7]
Q/Q
LEN
SET MIN
SET MAX
CASCADE
FTUNE
VCCO
Function
Signal Input
Input Enable
Mux Select Inputs
Signal Output
Latch Enable
Minimum Delay Set
Maximum Delay Set
Cascade Signal
Linear Voltage Input
VCC to Output
Rev.: E
Amendment: /0
1 Issue Date: October, 1998
1 page  
Micrel
APPLICATIONS INFORMATION
Analog Input Charateristics: Ftune = VCC to VEE
140
120
100
80
60
40
20
0
–4.5
–3.5 –2.5 –1.5
Ftune Voltage (V)
Propagation Delay vs Ftune Voltage (100E196)
–0.5
100
90
80
70
60
50
40
30
20
10
0
–5
–4 –3 –2 –1
Ftune Voltage (V)
Propagation Delay vs Ftune Voltage (10E196)
–0
ClockWorks™
SY10E196
SY100E196
5
5 Page | ||
| Páginas | Total 9 Páginas | |
| PDF Descargar | [ Datasheet SY100E196.PDF ] | |
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