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SY100E431 Schematic ( PDF Datasheet ) - Micrel Semiconductor

Teilenummer SY100E431
Beschreibung 3-BIT DIFFERENTIAL FLIP-FLOP
Hersteller Micrel Semiconductor
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Gesamt 4 Seiten
SY100E431 Datasheet, Funktion
3-BIT DIFFERENTIAL
FLIP-FLOP
SY10E431
SY100E431
FEATURES
s Differential D, clock and Q
s Extended 100E VEE range of –4.2V to –5.5V
s VBB output for single-ended use
s 1100MHz min. toggle frequency
s Edge-triggered asynchronous set and reset
s Fully compatible with Motorola MC10E/100E431
s Available in 28-pin PLCC package
BLOCK DIAGRAM
DESCRIPTION
The SY10/100E431 are 3-bit flip-flops with differential
clock, data input and data output.
The asynchronous Set and Reset controls are edge-
triggered rather than level controlled. This allows the user
to rapidly set or reset the flip-flop and then continue
clocking at the next clock edge without the necessity of
de-asserting the set/reset signal (as would be the case
with a level controlled set/reset).
The E431 is also designed with larger internal swings,
an approach intended to minimize the time spent crossing
the threshold region and thus reduces the metastability
susceptibility window.
S0
D0
D0
CLK0
CLK0
R0
S1
D1
D1
CLK1
CLK1
R1
S2
D2
D2
CLK2
CLK2
R2
S
DQ
Q
R
Q0
Q0
S
DQ
Q
R
Q1
Q1
S
DQ
Q
R
Q2
Q2
PIN CONFIGURATION
CLK1
CLK1
R1
VEE
S1
D1
D1
25 24 23 22 21 20 19
26 18
27 17
28 TOP VIEW 16
1
PLCC
15
2
J28-1
14
3 13
4 12
5 6 7 8 9 10 11
Q2
Q2
VCC
Q1
Q1
Q0
Q0
PIN NAMES
VBB
TRUTH TABLE(1)
Dn CLKn
LZ
HZ
XL
XL
NOTE:
1. Z = LOW-to-HIGH transition.
Rn
L
L
Z
L
Sn
L
L
L
Z
Pin Function
D[0:2], D[0:2]
Differential Data Inputs
CLK[0:2], CLK[0:2] Differential Clock Inputs
Qn S[0:2]
L R[0:2]
H VBB
L Q[0:2], Q[0:2]
H VCCO
Edge Triggered Set Inputs
Edge Triggered Reset Inputs
VBB Reference Output
Differential Data Outputs
VCC to Output
Rev.: C Amendment: /1
1 Issue Date: February, 1998





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