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SY100E445 Schematic ( PDF Datasheet ) - Micrel Semiconductor

Teilenummer SY100E445
Beschreibung 4-BIT SERIAL-to-PARALLEL CONVERTER
Hersteller Micrel Semiconductor
Logo Micrel Semiconductor Logo 




Gesamt 8 Seiten
SY100E445 Datasheet, Funktion
4-BIT SERIAL-to-PARALLEL
CONVERTER
SY10E445
SY100E445
FEATURES
s On-chip clock ÷4 and ÷8
s Extended 100E VEE range of –4.2V to –5.5V
s 2.5Gb/s data rate capability
s Differential clock and serial inputs
s VBB output for single-ended use
s Asynchronous data synchronization
s Mode select to expand to 8 bits
s Internal 75kinput pull-down resistors
s Fully compatible with Motorola MC10E/100E445
s Available in 28-pin PLCC package
PIN CONFIGURATION
SINB
SINB
SEL
VEE
CLK
CLK
VBB
25 24 23 22 21 20 19
26 18
27 17
28 16
TOP VIEW
1
PLCC
15
2
J28-1
14
3 13
4 12
5 6 7 8 9 10 11
SOUT
SOUT
VCC
Q0
Q1
VCCO
Q2
PIN NAMES
Pin
SINA, SINA
SINB, SINB
SEL
SOUT, SOUT
Q0–Q3
CLK, CLK
CL/4, CL/4
CL/8, CL/8
MODE
SYNC
RESET
VCCO
Function
Differential Serial Data Input A
Differential Serial Data Input B
Serial Input Select Pin
Differential Serial Data Output
Parallel Data Outputs
Differential Clock Inputs
Differential ÷4 Clock Output
Differential ÷8 Clock Output
Conversion Mode 4-bit/8-bit
Conversion Synchronizing Input
Input, Resets the Counters
VCC to Output
DESCRIPTION
The SY10/100E445 are integrated 4-bit serial-to-parallel
data converters. The devices are designed to operate for
NRZ data rates of up to 2.5Gb/s. The chip generates a
divide-by-4 and a divide-by-8 clock for both 4-bit conversion
and a two-chip 8-bit conversion function. The conversion
sequence was chosen to convert the first serial bit to Q0,
the second to Q1, etc.
Two selectable serial inputs provide a loopback capability
for testing purposes when the device is used in conjunction
with the E446 parallel-to-serial converter.
The start bit for conversion can be moved using the
SYNC input. A single pulse, applied asynchronously for at
least two input clock cycles, shifts the start bit for conversion
from Qn to Qn-1 by one bit. For each additional shift required,
an additional pulse must be applied to the SYNC input.
Asserting the SYNC input will force the internal clock dividers
to "swallow" a clock pulse, effectively shifting a bit from the
Qn to the Qn-1 output (see Timing Diagram B).
The MODE input is used to select the conversion mode
of the device. With the MODE input LOW (or open) the
device will function as a 4-bit converter. When the mode
input is driven HIGH, the data on the output will change on
every eighth clock cycle, thus allowing for an 8-bit conversion
scheme using two E445s. When cascaded in an 8-bit
conversion scheme, the devices will not operate at the
2.5Gb/s data rate of a single device. Refer to the applications
section of this data sheet for more information on cascading
the E445.
For lower data rate applications, a VBB reference voltage
is supplied for single-ended inputs. When operating at clock
rates above 500MHz, differential input signals are
recommended. For single-ended inputs, the VBB pin is tied
to the inverting differential input and bypassed via a 0.01µF
capacitor. The VBB provides the switching reference for the
input differential amplifier. The VBB can also be used to AC
couple an input signal.
Rev.: D Amendment: /0
1 Issue Date: October, 1998






SY100E445 Datasheet, Funktion
Micrel
Clock
Clock
Serial Input
Data
E445a
SIN SOUT
SIN SOUT
Q3 Q2 Q1 Q0
E445b
SIN
SIN
Q3 Q2 Q1 Q0
Q7 Q6 Q5 Q4
Q3 Q2 Q1 Q0
Parallel Output Data
Clock a
Clock b
Tpd CLK
to SOUT
667ps
(1.5GHz)
100ps
800ps
1050ps
Figure 4. Extended Frequency 1:8 Demultiplexer
SY10E445
SY100E445
CLK
SINa
Q0
Q1
Q2
Q3
Q4 (Q0 a)
Q5 (Q1 a)
Q6 (Q2 a)
Q7 (Q3 a)
SOUTa
SOUTb
CL/4a
CL/4b
CL/8a
CL/8b
Dn4
Dn3
Dn2
Dn1
Dn
Dn+1 Dn+2
Dn+3
Dn+4
Dn4
Dn3 Dn2
Dn1
Dn4
Dn
Dn3
Dn+1
Dn2
Dn4
Dn3
Dn2
Dn1
Dn
Dn+1
Dn+2
Dn+3
Dn+2 Dn+3
Dn1
Dn
Dn+1
Timing Diagram
PRODUCT ORDERING CODE
Ordering
Code
SY10E445JC
SY10E445JCTR
SY100E445JC
SY100E445JCTR
Package
Type
J28-1
J28-1
J28-1
J28-1
Operating
Range
Commercial
Commercial
Commercial
Commercial
6

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