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SY100E446 Schematic ( PDF Datasheet ) - Micrel Semiconductor

Teilenummer SY100E446
Beschreibung 4-BIT PARALLEL-TO-SERIAL CONVERTER
Hersteller Micrel Semiconductor
Logo Micrel Semiconductor Logo 




Gesamt 8 Seiten
SY100E446 Datasheet, Funktion
4-BIT PARALLEL-TO-SERIAL
CONVERTER
SY10E446
SY100E446
FEATURES
s On-chip clock ÷4 and ÷8
s Extended 100E VEE range of –4.2V to –5.5V
s 1.6Gb/s typical data rate capability
s Differential clock and serial inputs
s VBB output for single-ended use
s Asynchronous data synchronization
s Mode select to expand to 8 bits
s Internal 75Kinput pulldown resistors
s Fully compatible with Motorola MC10E/100E446
s Available in 28-pin PLCC package
PIN CONFIGURATION
CLK
CLK
VBB
VEE
SIN
SIN
SYNC
25 24 23 22 21 20 19
26 18
27 17
28
TOP VIEW
16
1
PLCC
15
2
J28-1
14
3 13
4 12
5 6 7 8 9 10 11
NC
NC
VCC
SOUT
SOUT
VCCO
NC
DESCRIPTION
The SY10/100E446 are integrated 4-bit parallel-to-
serial data converters. These devices are designed to
operate for NRZ data rates of up to a minimum of 1.3Gb/
s. The chips generate a divide-by-4 and a divide-by-8
clock for both 4-bit conversion and a two-chip 8-bit
conversion function. The conversion sequence was
chosen to convert the parallel data into a serial stream
from bit D0 to D3. A serial input is provided to cascade
two E446 devices for 8-bit conversion applications.
The SYNC input will asynchronously reset the internal
clock circuitry. This pin allows the user to reset the internal
clock conversion unit and, thus, select the start of the
conversion process.
The MODE input is used to select the conversion mode
of the device. With the MODE input LOW (or open) the
device will function as a 4-bit converter. When the mode
input is driven HIGH, the internal load clock will change
on every eighth clock cycle, thus allowing for an 8-bit
conversion scheme using two E446s. When cascaded in
an 8-bit conversion scheme, the devices will not operate
at the 1.3Gb/s data rate of a single device. Refer to the
applications section of this data sheet for more information
on cascading the E446.
For lower data rate applications, a VBB reference
voltage is supplied for single-ended inputs. When
operating at clock rates above 500MHz, differential input
signals are recommended. For single-ended inputs, the
VBB pin is tied to the inverting differential input and
bypassed via a 0.01µF capacitor. The VBB provides the
switching reference for the input differential amplifier. The
VBB can also be used to AC couple an input signal.
PIN NAMES
Pin
SIN, SIN
D0 – D3
SOUT, SOUT
CLK, CLK
CL/4, CL/4
CL/8, CL/8
MODE
SYNC
VCCO
Function
Differential Serial Data Input
Parallel Data Input
Differential Serial Data Output
Differential Clock Input
Differential 4 Clock Output
Differential 8 Clock Output
Conversion Mode, 4-bit/8-bit
Conversion Synchronizing Input
VCC to Output
Rev.: C
Amendment: /1
1 Issue Date: February, 1998






SY100E446 Datasheet, Funktion
Micrel
SY10E446
SY100E446
APPLICATIONS INFORMATION
The SY10E/100E446 are integrated 4:1 parallel-to-serial
converters. The chips are designed to work with the E445
device to provide both transmission and receiving of a high-
speed serial data path. The E446 can convert 4 bits of
data into a 1.3Gb/s NRZ data stream. The device features
a SYNC input which allows the user to reset the internal
clock circuitry and restart the conversion sequence (see
Timing Diagram A). Note that SOUT is triggered by negative
clock edges.
The E446 features a differential serial input and internal
divide-by-eight circuitry to facilitate the cascading of two
devices to build an 8:1 multiplexer. Figure 1 illustrates the
architecture for an 8:1 multiplexer using two E446s (see
Timing Diagram B). Notice the serial outputs (SOUT) of the
lower order converter feed the serial inputs of the higher
order device. This feed through of the serial inputs bounds
the upper end of the frequency of operation. The clock-to-
serial output propagation delay, plus the set-up time of the
serial input pins, must fit into a single clock period for the
cascade architecture to function properly. Using the worst
case values for these two parameters from the data sheet,
tPD CLK to SOUT = 1600ps and ts for SIN = 200ps, yields
a minimum period of 1400ps or a clock frequency of
700MHz.
The clock frequency is somewhat lower than that of a
single converter. In order to increase this frequency, it is
recommended that the clock edge feeding the E446A be
delayed with respect to the E446B, as shown in Figure 2.
Perhaps the easiest way to delay the second clock relative
to the first is to take advantage of the differential clock
inputs of the E446. By connecting the clock for E446A to
the complimentary clock input pin, the device will clock a
half a clock period after E446B (Figure 2). Utilizing this
simple technique will raise the potential conversion frequency
up to the maximum 1.3GHz of a stand-alone E446.
CLK
CLK
CLK
tPD
CLK to SOUT
E446B
SOUT
SOUT
E446A
SIN SOUT
SIN SOUT
SERIAL
DATA
D3 D2 D1 D0
D3 D2 D1 D0
D7 D6 D5 D4
D3 D2 D1 D0
PARALLEL DATA
1400ps
200ps
1600ps
Figure 1. Cascaded 8:1 Converter Architecture
6

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