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PDF SY100E337 Data sheet ( Hoja de datos )
| Número de pieza | SY100E337 | |
| Descripción | 3-BIT SCANNABLE | |
| Fabricantes | Micrel Semiconductor | |
| Logotipo |  |
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3-BIT SCANNABLE
REGISTERED BUS
TRANSCEIVER
SY10E337
SY100E337
FEATURES
s 1500ps max. clock to bus (data transmit)
s 1000ps max. clock to Q (data receive)
s Extended 100E VEE range of –4.2V to –5.5V
s 25Ω cutoff bus outputs
s 50Ω receiver outputs
s Scannable implementation of E336
s Synchronous and asynchronous bus enables
s Non-inverting data path
s Bus outputs feature internal edge slow-down
capacitors
s Additional package ground pins
s Fully compatible with industry standard 10KH,
100K ECL levels
s Internal 75KΩ input pulldown resistors
s Fully compatible with Motorola MC10E/100E337
s Available in 28-pin PLCC package
PIN CONFIGURATION
SCAN
S-IN
TEN
VEE
REN
CLK
A1
25 24 23 22 21 20 19
26 18
27 17
28
TOP VIEW
16
1
PLCC
15
J28-1
2 14
3 13
4 12
5 6 7 8 9 10 11
GND
BUS0
VCC
Q1
VCCO
BUS1
GND
DESCRIPTION
The SY10/100E337 are 3-bit registered bus transceivers
with scan designed for use in new, high- performance ECL
systems. The bus outputs (BUS0–BUS2) are designed to
drive a 25Ω bus; the receive outputs (Q0–Q2) are designed
for 50Ω. The bus outputs feature a normal logic HIGH level
(VOH) and a cutoff LOW level of –2.0V and the output
emitter-follower is “off”, presenting a high impedance to the
bus. The bus outputs also feature edge slow-down
capacitors.
Both drive and receive sides feature the same logic,
including a loopback path to hold data. The LOAD/HOLD
function is controlled by Transmit Enable (TEN) and Receive
Enable (REN) on the transmit and receive sides,
respectively, with a HIGH selecting LOAD. The
implementation of the E337 Receive Enable differs from
that of the E336.
A synchronous bus enable (SBUSEN) is provided for
normal, non-scan operation. The asynchronous bus disable
(ABUSDIS) disables the bus for scan mode.
The SYNCEN input allows either synchronous or
asynchronous re-enabling after disabling with ABUSDIS.
An alternative use is asynchronous-only operation with
ABUSDIS, in which case SYNCEN is tied LOW. SYNCEN
is implemented as an overriding SET control to the enable
flip-flop.
Scan mode is selected by a logic HIGH at the SCAN
input. Scan input data is shifted in through S-IN, and output
data appears at the Q2 output.
All registers are clocked on the rising edge of CLK.
Additional lead-frame grounding is provided through the
ground pins (GND) which should be connected to 0V. The
GND pins are not electrically connected to the chip.
PIN NAMES
Pin
A0–A2
B0–B2
S-IN
TEN, REN
SCAN
ABUSDIS
SBUSEN
SYNCEN
CLK
BUS0–BUS2
Q0–Q2
VCCO
Function
Data Inputs A
Data Inputs B
Serial (Scan) Data Input
LOAD/HOLD Controls
Scan Control
Asynchronous Bus Disable
Synchronous Bus Enable
Synchronous Enable Control
Clock
25Ω Cutoff BUS Outputs
Receive Data Outputs (Q2 serves as
SCAN_OUT in scan mode)
VCC to Output
Rev.: C Amendment: /2
1 Issue Date: February, 1998
1 page | ||
| Páginas | Total 4 Páginas | |
| PDF Descargar | [ Datasheet SY100E337.PDF ] | |
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