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PDF SY100EL34L Data sheet ( Hoja de datos )
| Número de pieza | SY100EL34L | |
| Descripción | 5V/3.3V /2 /4 /8 CLOCK GENERATION CHIP | |
| Fabricantes | Micrel Semiconductor | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de SY100EL34L (archivo pdf) en la parte inferior de esta página. Total 4 Páginas | ||
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5V/3.3V ÷2, ÷4, ÷8 CLOCK
GENERATION CHIP
ClockWorks™
SY10EL34/L
SY100EL34/L
FEATURES
s 3.3V and 5V power supply options
s 50ps output-to-output skew
s Synchronous enable/disable
s Master Reset for synchronization
s Internal 75KΩ input pull-down resistors
s Available in 16-pin SOIC package
PIN CONFIGURATION/BLOCK DIAGRAM
Q0 1
Q0 2
VCC 3
Q1 4
Q1 5
VCC 6
Q2 7
Q2 8
Q
÷2
R
Q
÷4
R
Q
÷8
R
16 VCC
15 EN
QD
14 NC
R
13 CLK
12 CLK
11 VBB
10 MR
9 VEE
SOIC
TOP VIEW
DESCRIPTION
The SY10/100EL34/L are low skew ÷2, ÷4, ÷8 clock
generation chips designed explicitly for low skew clock
generation applications. The internal dividers are
synchronous to each other, therefore, the common output
edges are all precisely aligned. The devices can be driven
by either a differential or single-ended ECL or, if positive
power supplies are used, PECL input signal. In addition,
by using the VBB output, a sinusoidal source can be AC-
coupled into the device. If a single-ended input is to be
used, the VBB output should be connected to the CLK
input and bypassed to ground via a 0.01µF capacitor.
The VBB output is designed to act as the switching
reference for the input of the EL34/L under single-ended
input conditions. As a result, this pin can only source/
sink up to 0.5mA of current.
The common enable (EN) is synchronous so that the
internal dividers will only be enabled/disabled when the
internal clock is already in the LOW state. This avoids
any chance of generating a runt clock pulse on the
internal clock when the device is enabled/disabled as
can happen with an asynchronous control. An internal
runt pulse could lead to losing synchronization between
the internal divider stages. The internal enable flip-flop is
clocked on the falling edge of the divider stages. The
internal enable flip-flop is clocked on the falling edge of
the input clock, therefore, all associated specification
limits are referenced to the negative edge of the clock
input.
Upon start-up, the internal flip-flops will attain a random
state; the master reset (MR) input allows for the
synchronization of the internal dividers, as well as for
multiple EL34/Ls in a system.
PIN NAMES
Pin Function
CLK Differential Clock Inputs
EN Synchronous Enable
MR Master Reset
VBB Reference Output
Q0 Differential ÷2 Outputs
Q1 Differential ÷4 Outputs
Q2 Differential ÷8 Outputs
Rev.: F Amendment: /0
1 Issue Date: August, 1998
1 page | ||
| Páginas | Total 4 Páginas | |
| PDF Descargar | [ Datasheet SY100EL34L.PDF ] | |
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