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PDF SY100EL35 Data sheet ( Hoja de datos )
| Número de pieza | SY100EL35 | |
| Descripción | JK FLIP-FLOP | |
| Fabricantes | Micrel Semiconductor | |
| Logotipo |  |
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JK FLIP-FLOP
SY10EL35
SY100EL35
FEATURES
s 525ps propagation delay
s 2.2GHz toggle frequency
s High bandwidth output transistions
s Internal 75KΩ input pull-down resistors
s Available in 8-pin SOIC package
DESCRIPTION
The SY10/100EL35 are high-speed JK Flip-Flops. The
J/K data enters the master portion of the flip-flop when
the clock is LOW and is transferred to the slave and,
thus, the outputs, upon a positive transition of the clock.
The reset pin is asynchronous and is activated with a
logic HIGH.
PIN CONFIGURATION/BLOCK DIAGRAM
J1
K2
CLK 3
R4
J
K
R
8 VCC
7Q
6Q
5 VEE
SOIC
TOP VIEW
TRUTH TABLE(1)
JK
LL
LH
HL
HH
XX
NOTE:
1. Z = LOW-to-HIGH transition.
R
L
L
L
L
H
CLK
Z
Z
Z
Z
X
Qn+1
Qn
L
H
Qn
L
Rev.: E Amendment: /0
1 Issue Date: August, 1998
1 page | ||
| Páginas | Total 4 Páginas | |
| PDF Descargar | [ Datasheet SY100EL35.PDF ] | |
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