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ST62T15C Schematic ( PDF Datasheet ) - ST Microelectronics

Teilenummer ST62T15C
Beschreibung (ST62T15C / ST62T25C) 8-BIT OTP/EPROM MCUs WITH A/D CONVERTER
Hersteller ST Microelectronics
Logo ST Microelectronics Logo 




Gesamt 30 Seiten
ST62T15C Datasheet, Funktion
ST62T15C/T25C/E25C
8-BIT OTP/EPROM MCUs WITH A/D CONVERTER,
OSCILLATOR SAFEGUARD, SAFE RESET AND 28 PINS
s 3.0 to 6.0V Supply Operating Range
s 8 MHz Maximum Clock Frequency
s -40 to +125°C Operating Temperature Range
s Run, Wait and Stop Modes
s 5 Interrupt Vectors
s Look-up Table capability in Program Memory
s Data Storage in Program Memory:
User selectable size
s Data RAM: 64bytes
s User Programmable Options
s 20 I/O pins, fully programmable as:
– Input with pull-up resistor
– Input without pull-up resistor
– Input with interrupt generation
– Open-drain or push-pull output
– Analog Input
s 4 I/O lines can sink up to 20mA to drive LEDs or
TRIACs directly
s 8-bit Timer/Counter with 7-bit programmable
prescaler
s Digital Watchdog
s Oscillator Safe Guard
s Low Voltage Detector for Safe Reset
s 8-bit A/D Converter with 16 analog inputs
s On-chip Clock oscillator can be driven by Quartz
Crystal Ceramic resonator or RC network
s Power-on Reset
s One external Non-Maskable Interrupt
s ST626x-EMU2 Emulation and Development
System (connects to an MS-DOS PC via a
parallel port).
DEVICE SUMMARY
DEVICE
ST62T15C
ST62T25C
ST62E25C
OTP
(Bytes)
1836
3884
EPROM
(Bytes)
-
-
3884
I/O Pins
20
20
20
PDIP28
PS028
SS0P28
CDIP28W
(See end of Datasheet for Ordering Information)
August 1999
Rev. 2.8
1/70
1






ST62T15C Datasheet, Funktion
ST62T15C/T25C/E25C
1.3 MEMORY MAP
1.3.1 Introduction
The MCU operates in three separate memory
spaces: Program space, Data space, and Stack
space. Operation in these three memory spaces is
described in the following paragraphs.
Figure 3. Memory Addressing Diagram
Briefly, Program space contains user program
code in OTP and user vectors; Data space con-
tains user data in RAM and in OTP, and Stack
space accommodates six levels of stack for sub-
routine and interrupt service routine nesting.
0000h
PROGRAM SPACE
PROGRAM
MEMORY
0-63
0FF0h
0FFFh
INTERRUPT &
RESET VECTORS
DATA SPACE
000h
RAM / EEPROM
BANKING AREA
03Fh
040h
07Fh
080h
081h
082h
083h
084h
DATA READ-ONLY
MEMORY WINDOW
X REGISTER
Y REGISTER
V REGISTER
W REGISTER
RAM
0C0h
0FFh
DATA READ-ONLY
MEMORY
WINDOW SELECT
DATA RAM
BANK SELECT
ACCUMULATOR
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6

6 Page









ST62T15C pdf, datenblatt
ST62T15C/T25C/E25C
2 CENTRAL PROCESSING UNIT
2.1 INTRODUCTION
The CPU Core of ST6 devices is independent of the
I/O or Memory configuration. As such, it may be
thought of as an independent central processor
communicating with on-chip I/O, Memory and Pe-
ripherals via internal address, data, and control
buses. In-core communication is arranged as
shown in Figure 6; the controller being externally
linked to both the Reset and Oscillator circuits,
while the core is linked to the dedicated on-chip pe-
ripherals via the serial data bus and indirectly, for
interrupt purposes, through the control registers.
2.2 CPU REGISTERS
The ST6 Family CPU core features six registers and
three pairs of flags available to the programmer.
These are described in the following paragraphs.
Accumulator (A). The accumulator is an 8-bit
general purpose register used in all arithmetic cal-
culations, logical operations, and data manipula-
tions. The accumulator can be addressed in Data
space as a RAM location at address FFh. Thus the
ST6 can manipulate the accumulator just like any
other register in Data space.
Figure 6. ST6 Core Block Diagram
Indirect Registers (X, Y). These two indirect reg-
isters are used as pointers to memory locations in
Data space. They are used in the register-indirect
addressing mode. These registers can be ad-
dressed in the data space as RAM locations at ad-
dresses 80h (X) and 81h (Y). They can also be ac-
cessed with the direct, short direct, or bit direct ad-
dressing modes. Accordingly, the ST6 instruction
set can use the indirect registers as any other reg-
ister of the data space.
Short Direct Registers (V, W). These two regis-
ters are used to save a byte in short direct ad-
dressing mode. They can be addressed in Data
space as RAM locations at addresses 82h (V) and
83h (W). They can also be accessed using the di-
rect and bit direct addressing modes. Thus, the
ST6 instruction set can use the short direct regis-
ters as any other register of the data space.
Program Counter (PC). The program counter is a
12-bit register which contains the address of the
next ROM location to be processed by the core.
This ROM location may be an opcode, an oper-
and, or the address of an operand. The 12-bit
length allows the direct addressing of 4096 bytes
in Program space.
RE SET
0,01 TO 8MHz
OSCin
OSCout
CONTR OLLER
INTERRUPTS
DATA SPACE
OPCODE
FLAG
VALUES
2
CONTROL
SIGNALS
ADDRESS /READ LINE
DATA
RAM/EEPR OM
PROGRAM
ROM/EPRO M
12
Program Counter
and
6 LAYER STACK
ADDRESS 256
DECODER
DATA
ROM/EP ROM
A-DATA B-DATA
DEDICAT IONS
A CCUMULATO R
FLAGS
ALU
RESULTS TO DATA SPACE (WRITE LINE)
VR01811
12/70
12

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