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ST6215C Schematic ( PDF Datasheet ) - ST Microelectronics

Teilenummer ST6215C
Beschreibung 8-BIT MCUs
Hersteller ST Microelectronics
Logo ST Microelectronics Logo 




Gesamt 30 Seiten
ST6215C Datasheet, Funktion
ST6215C ST6225C
8-bit MCUs with A/D converter,
two timers, oscillator safeguard & safe reset
Memories
– 2K or 4K bytes Program memory (OTP,
EPROM, FASTROM or ROM) with read-out
protection
– 64 bytes RAM
Clock, Reset and Supply Management
– Enhanced reset system
– Low Voltage Detector (LVD) for Safe Reset
– Clock sources: crystal/ceramic resonator or
RC network, external clock, backup oscillator
(LFAO)
– Oscillator Safeguard (OSG)
– 2 Power Saving Modes: Wait and Stop
Interrupt Management
– 4 interrupt vectors plus NMI and RESET
– 20 external interrupt lines (on 2 vectors)
– 1 external non-interrupt line
20 I/O Ports
– 20 multifunctional bidirectional I/O lines
– 16 alternate function lines
– 4 high sink outputs (20mA)
2 Timers
– Configurable watchdog timer
– 8-bit timer/counter with a 7-bit prescaler
Analog Peripheral
– 8-bit ADC with 16 input channels
Instruction Set
– 8-bit data manipulation
– 40 basic instructions
– 9 addressing modes
– Bit manipulation
Device Summary
Features
Program memory - bytes
RAM - bytes
Operating Supply
Clock Frequency
Operating Temperature
Packages
ST6215C
2K
PDIP28
S028
SS0P28
CDIP28W
(See Section 12.5 for Ordering Information)
Development Tools
– Full hardware/software development package
64
3.0V to 6V
8MHz Max
-40°C to +125°C
PDIP28 / SO28 / SSOP28
ST6225C
4K
January 2009
Rev 4
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1






ST6215C Datasheet, Funktion
ST6215C ST6225C
1 INTRODUCTION
The ST6215C, 25C devices are low cost members
of the ST62xx 8-bit HCMOS family of microcontrol-
lers, which is targeted at low to medium complexity
applications. All ST62xx devices are based on a
building block approach: a common core is sur-
rounded by a number of on-chip peripherals.
The ST62E25C is the erasable EPROM version of
the ST62T15C, T25C devices, which may be used
during the development phase for the ST62T15C,
T25C target devices, as well as the respective
ST6215C, 25C ROM devices.
OTP and EPROM devices are functionally identi-
cal. OTP devices offer all the advantages of user
programmability at low cost, which make them the
ideal choice in a wide range of applications where
frequent code changes, multiple code versions or
last minute programmability are required.
The ROM based versions offer the same function-
ality, selecting the options defined in the program-
Figure 1. Block Diagram
mable option bytes of the OTP/EPROM versions
in the ROM option list (See Section 12.6 on page
97).
The ST62P15C/P25C are the Factory Advanced
Service Technique ROM (FASTROM) versions of
ST62T15C,T25C OTP devices.
They offer the same functionality as OTP devices,
but they do not have to be programmed by the
customer (See Section 12 on page 91).
These compact low-cost devices feature a Timer
comprising an 8-bit counter with a 7-bit program-
mable prescaler, an 8-bit A/D Converter with 16
analog inputs and a Digital Watchdog timer, mak-
ing them well suited for a wide range of automo-
tive, appliance and industrial applications.
For easy reference, all parametric data is located
in Section 11 on page 63.
8-BIT
A/D CONVERTER
VPP
NMI INTERRUPTS
P:ROGRAM
MEMORY
(2K or 4K Bytes)
DATA ROM
USER
SELECTABLE
DATA RAM
64 Bytes
PC
STACK LEVEL 1
STACK LEVEL 2
STACK LEVEL 3
STACK LEVEL 4
STACK LEVEL 5
STACK LEVEL 6
8-BIT CORE
POWER
SUPPLY
OSCILLATOR
RESET
PORT A
PORT B
PORT C
PA0..PA3 (20mA Sink)
PA4..PA7 / Ain
PB0..PB7 / Ain
PC4..PC7 / Ain
TIMER
WATCHDOG
TIMER
TIMER
VDD VSS OSCin OSCout RESET
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ST6215C pdf, datenblatt
ST6215C ST6225C
MEMORY MAP (Cont’d)
Table 2. Hardware Register Map
Address
080h
to 083h
0C0h
0C1h
0C2h
0C3h
0C4h
0C5h
0C6h
0C7h
0C8h
0C9h
0CAh
0CBh
0CCh
0CDh
0CEh
Block
CPU
I/O Ports
I/O Ports
CPU
ROM
I/O Ports
Register
Label
Register Name
X,Y,V,W
DRA 1) 2) 3)
DRB 1) 2) 3)
DRC 1) 2) 3)
DDRA 2)
DDRB 2)
DDRC 2)
IOR
DRWR
X,Y index registers
V,W short direct registers
Port A Data Register
Port B Data Register
Port C Data Register
Reserved (1 Byte)
Port A Direction Register
Port B Direction Register
Port C Direction Register
Reserved (1 Byte)
Interrupt Option Register
Data ROM Window register
ORA 2)
ORB 2)
ORC 2)
Reserved (2 Bytes)
Port A Option Register
Port B Option Register
Port C Option Register
Reset
Status
Remarks
xxh R/W
00h R/W
00h R/W
00h R/W
00h R/W
00h R/W
00h R/W
xxh Write-only
xxh Write-only
00h R/W
00h R/W
00h R/W
0CFh
Reserved (1 byte)
0D0h
0D1h
ADC
ADR
ADCR
A/D Converter Data Register
A/D Converter Control Register
xxh Read-only
40h Ro/Wo
0D2h
0D3h
0D4h
Timer1
PSCR
TCR
TSCR
Timer 1 Prescaler Register
Timer 1 Counter Register
Timer 1 Status Control Register
7Fh
0FFh
00h
R/W
R/W
R/W
0D5h
to 0D7h
Reserved (3 Bytes)
0D8h
Watchdog
Timer
WDGR
Watchdog Register
0FEh R/W
0D9h
to 0FEh
Reserved (38 Bytes)
0FFh
CPU
A
Accumulator
xxh R/W
Legend:
x = undefined, R/W = Read/Write, Ro = Read-only Bit(s) in the register, Wo = Write-only Bit(s)
in the register.
Notes:
1. The contents of the I/O port DR registers are readable only in output configuration. In input configura-
tion, the values of the I/O pins are returned instead of the DR register contents.
2. The bits associated with unavailable pins must always be kept at their reset value.
3. Do not use single-bit instructions (SET, RES...) on Port Data Registers if any pin of the port is configured
in input mode (refer to Section 8 "I/O PORTS" on page 38 for more details).
12/105
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