ST62E18C Schematic ( PDF Datasheet ) - ST Microelectronics

Teilenummer	ST62E18C
Beschreibung	8-BIT MCUs WITH A/D CONVERTER
Hersteller	ST Microelectronics
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Gesamt 70 Seiten ST62T18C/E18C 8-BIT MCUs WITH A/D CONVERTER, AUTO-RELOAD TIMER, UART, OSG, SAFE RESET AND 20-PIN PACKAGE s 3.0 to 6.0V Supply Operating Range s 8 MHz Maximum Clock Frequency s -40 to +125°C Operating Temperature Range s Run, Wait and Stop Modes s 5 Interrupt Vectors s Look-up Table capability in Program Memory s Data Storage in Program Memory: User selectable size s Data RAM: 192 bytes s User Programmable Options s 12 I/O pins, fully programmable as: – Input with pull-up resistor – Input without pull-up resistor – Input with interrupt generation – Open-drain or push-pull output – Analog Input s 5 I/O lines can sink up to 20mA to drive LEDs or TRIACs directly s 8-bit Timer/Counter with 7-bit programmable prescaler s 8-bit Auto-reload Timer with 7-bit programmable prescaler (AR Timer) s Digital Watchdog s 8-bit A/D Converter with 7 analog inputs s 8-bit Asynchronous Peripheral Interface (UART) s On-chip Clock oscillator can be driven by Quartz Crystal or Ceramic resonator s Oscillator Safe Guard s Low Voltage Detector for safe Reset s One external Non-Maskable Interrupt s ST623x-EMU2 Emulation and Development System (connects to an MS-DOS PC via a parallel port). DEVICE SUMMARY DEVICE ST62T18C ST62E18C OTP (Bytes) 7948 EPROM (Bytes) - 7948 I/O Pins 12 12 PDIP20 PSO20 CDIP20W (See end of Datasheet for Ordering Information) November 1999 Rev. 2.5 1/82 1 ST62T18C/E18C INTRODUCTION (Cont’d) OTP and EPROM devices are functionally identi- cal. The ROM based versions offer the same func- tionality selecting as ROM options the options de- fined in the programmable option byte of the OTP/ EPROM versions.OTP devices offer all the advan- tages of user programmability at low cost, which make them the ideal choice in a wide range of ap- plications where frequent code changes, multiple code versions or last minute programmability are required. Figure 2. ST62T18C/E18C Pin Configuration These compact low-cost devices feature a Timer VDD 1 TIMER 2 20 VSS 19 PA1* OSCin 3 18 PA2/ARTIMout* OSCout 4 17 PA3/ARTIMin* NMI TES T/VPP(1) RESET 5 6 7 16 PA4* 15 PA5* 14 PD4/Ain/RXD1 Ain/PB6 8 13 PD5/Ain/TXD1 Ain/PB5 9 12 PD6/Ain Ain/PB4 10 11 PD7/Ain (1) V on EPROM/OTP only PP (*) 20 mA Sink 6/82 6 6 Page ST62T18C/E18C MEMORY MAP (Cont’d) 1.3.6 Data RAM Bank Register (DRBR) Address: CBh — Write only 7 - - - DRBR4 DRBR3 - - 0 - Bit 7-5 = These bits are not used Bit 4 - DRBR4. This bit, when set, selects RAM Page 2. Bit 3 - DRBR3. This bit, when set, selects RAM Page 1. Bit 2.0 These bits are not used. The selection of the bank is made by programming the Data RAM Bank Switch register (DRBR regis- ter) located at address CBh of the Data Space ac- cording to Table 1. No more than one bank should be set at a time. The DRBR register can be addressed like a RAM Data Space location at the address CBh; never- theless it is a write only register that cannot be ac- cessed with single-bit operations. This register is used to select the desired 64-byte RAM bank of the Data Space. The number of banks has to be loaded in the DRBR register and the instruction has to point to the selected location as if it was in bank 0 (from 00h address to 3Fh address). This register is not cleared during the MCU initiali- zation, therefore it must be written before the first access to the Data Space bank region. Refer to the Data Space description for additional informa- tion. The DRBR register is not modified when an interrupt or a subroutine occurs. Notes: Care is required when handling the DRBR register as it is write only. For this reason, it is not allowed to change the DRBR contents while executing in- terrupt service routine, as the service routine can- not save and then restore its previous content. If it is impossible to avoid the writing of this register in interrupt service routine, an image of this register must be saved in a RAM location, and each time the program writes to DRBR it must write also to the image register. The image register must be written first, so if an interrupt occurs between the two instructions the DRBR is not affected. In DRBR Register, only 1 bit must be set. Other- wise two or more pages are enabled in parallel, producing errors. Table 5. Data RAM Bank Register Set-up DRBR 00h 01h 02h 08h 10h other ST62T18C/E18C None Reserved Reserved RAM Page 1 RAM Page 2 Reserved 12/82 12 12 Page
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